TFT Substrate Gate Orientation for Polysilicon Uniformity
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Solution Overview
Problem
The anisotropic crystallization form of polysilicon in TFTs leads to variations in electrical characteristics, causing mura effects and reduced display quality due to differing channel region orientations in TFTs across the substrate, affecting carrier mobility and uniformity.
Innovation Solution
The TFT array substrate design includes a semiconductor island with sub-grain boundaries (SGBs) and a gate structure where the included angles between the gate and carrier migration paths are optimized, ensuring the carrier path crosses multiple SGBs, thereby reducing anisotropic effects and enhancing uniformity. Additionally, the channel region is extended along a curve to maintain consistent width, allowing carriers to traverse multiple SGBs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon crystallization is performed using conventional SLS laser crystallization, then carrier mobility is improved, but anisotropic crystallization form causes variations in electrical characteristics and mura effects
Solution Approach 1:
The patent applies asymmetry by intentionally designing the channel region orientation to be non-perpendicular (at angles of 10-80 degrees) relative to the sub-grain boundaries, rather than using conventional perpendicular orientations. This asymmetric angular relationship between channel regions and SGBs reduces the anisotropic effects that cause mura, while still maintaining adequate carrier mobility through the polysilicon crystallization structure
Solution Approach 2:
The patent changes the angular parameter of channel region orientation relative to sub-grain boundaries from conventional perpendicular (90 degrees) to non-perpendicular angles (10-80 degrees). This parameter modification transforms the crystallization-anisotropy relationship, reducing mura effects while preserving electrical performance through optimized angular geometry
2Reliability
If channel regions are oriented perpendicular to sub-grain boundaries, then carrier mobility is maximized, but electrical property uniformity deteriorates due to anisotropic crystallization
Solution Approach 1:
The patent deliberately introduces asymmetry by orienting channel regions at non-perpendicular angles (10-80 degrees) to sub-grain boundaries. This asymmetric configuration reduces the sensitivity to crystallization anisotropy, achieving more uniform electrical properties across the display region while maintaining acceptable carrier mobility through the polysilicon structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the uniformity of electrical properties across the TFT array substrate, reducing variations in carrier mobility and enhancing display quality by minimizing the impact of crystallization form anisotropy on TFT performance.
Implementation Method 1
a laser beam is irradiated to melt a whole surface of the amorphous silicon layer
Implementation Method 2
regions of film sequential lateral solidification and grain boundary locations
Data Source
AI summary
A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided.