Stacked Semiconductor Memory Layout for Arcing Isolation
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Solution Overview
Problem
Current stacked semiconductor memory devices face challenges in downsizing due to the need for a thick insulating film between the semiconductor substrate and memory cells, and forming a control circuit inside the insulating film, which affects the integration and performance of memory cells.
Innovation Solution
A semiconductor memory device design that includes a semiconductor substrate with a diode in the upper layer, a conductive film connected to the diode, a stacked body with alternating insulator and electrode films, and a charge storage member between the electrode film and a semiconductor member, allowing for efficient integration and operation of memory cells while preventing arcing and breakdown of insulating films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a thick insulating film is provided between the semiconductor substrate and memory cells to enable downsizing, then the integration density is improved, but the risk of arcing and breakdown increases
Solution Approach 1:
A ground potential electrode is introduced as an intermediary component between the high-voltage control circuit and the memory cells. This electrode acts as a shield that intercepts and dissipates electrical discharge, preventing arcing between the control circuit and memory cells while enabling the use of thick insulating films for downsizing.
Solution Approach 2:
The ground potential electrode is positioned in advance between the control circuit and memory cells to provide protective cushioning against potential electrical breakdown. This preventive structure absorbs and redirects electrical stress before it can cause damage to the insulating film or adjacent components.
2Area of stationary object
If control circuits are formed inside the insulating film and upper layer portion to achieve further downsizing, then the device area is reduced, but the electrical interference and parasitic capacitance increase
Solution Approach 1:
The device is segmented into distinct electrical zones by the ground potential electrode, which separates the control circuit region from the memory cell region. This segmentation creates electrical isolation that reduces parasitic capacitance between the control circuits and memory cells while maintaining compact device area.
Solution Approach 2:
The ground potential electrode serves as an electrical intermediary that blocks capacitive coupling between the control circuits embedded in the insulating film and the memory cells. By providing a grounded reference plane, it minimizes unwanted electrical interference and parasitic effects.
3Ease of operation
If a conductive film is provided on the insulating film to serve as source line, then the connectivity is improved, but the electrical independence from substrate is reduced
Solution Approach 1:
The ground potential electrode acts as an intermediary that decouples the source line (conductive film on insulating film) from the semiconductor substrate. This allows the source line to maintain its connectivity function while achieving electrical independence from the substrate, enabling flexible voltage control and reduced substrate interference.
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.