Self-Timed Conditional Logic Circuits With Pipelined Select Routing
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Solution Overview
Problem
Designing reliable clock networks for large programmable integrated circuits (ICs) with multiple clock domains is resource-intensive and challenging due to timing requirements, skew, jitter, and variability in process, voltage, and temperature, which complicates the implementation of efficient and flexible logic blocks for compute-intensive applications.
Innovation Solution
The implementation of self-timed circuits with pipelined routing paths and programmable logic blocks allows for conditional statements and optimized logic operations, enabling flexible and efficient logic block design by decoupling the number of pipeline stages from the shared logic circuit stages, thus improving the regularity and efficiency of programmable ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock networks are used in large programmable ICs, then timing control can be achieved, but design complexity and resource consumption increase significantly
Solution Approach 1:
The circuit uses self-timed logic where the logic blocks themselves generate and control their own timing signals through enable inputs and internal state machines, eliminating the need for external clock networks to provide timing control. Each logic block autonomously manages its own operation timing based on data arrival and completion signals.
Solution Approach 2:
The patent extracts the timing control function from the traditional clock network and relocates it to the individual logic blocks. By removing the global clock distribution network and placing timing control within each logic block, the design complexity of the clock network is significantly reduced while maintaining reliable timing control.
2Device complexity
If self-timed circuits are used, then design complexity is reduced, but timing synchronization between logic blocks becomes challenging
Solution Approach 1:
The circuit implements feedback mechanisms where completion signals from logic blocks feed back to the interconnect structure and subsequent logic blocks. This feedback allows automatic timing synchronization without external clock control, as each block waits for confirmation that previous blocks have completed their operations before proceeding.
Solution Approach 2:
The interconnect structure is designed to preliminarily route and buffer signals between logic blocks, ensuring that data is ready and synchronized before reaching the next logic block. This preliminary preparation of signals maintains timing synchronization without requiring complex external timing control.
3Adaptability or versatility
If multiple clock domains are implemented, then functional flexibility is improved, but skew and jitter issues worsen
Solution Approach 1:
Each logic block independently generates its own timing enable signals based on its operational needs and data arrival times, rather than being driven by external clock domains. This self-service approach eliminates skew and jitter problems associated with multiple clock domains while maintaining the ability to support multiple functional operating modes.
4Adaptability or versatility
If conditional statements are implemented in traditional logic blocks, then computational flexibility is improved, but regularity of the logic block structure deteriorates
Solution Approach 1:
The logic block is segmented into distinct functional units: a programmable logic unit for computing, a separate control unit for managing conditional execution, and an interconnect interface. This segmentation allows conditional statements to be implemented through control signals rather than irregular logic structures, maintaining the regularity of the overall logic block array while providing computational flexibility.
Data Source
AI summary
An exemplary circuit for implementing conditional statements in self-timed logic circuits includes first and second logic circuits, an input circuit, an output circuit, and a pipelined routing path. The first and second logic circuits each have a self-timed input and a self-timed output. The input circuit is coupled to provide a self-timed input signal to the self-timed input of a selected one of the first or second logic circuits based on the value of a control signal, and is further coupled to output a self-timed select signal. The output circuit is coupled to receive the self-timed output from the first logic circuit and the self-timed output from the second logic circuit, and to output a selected one of the self-timed outputs based on a value of the self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit.