Embedded Flash Gate Structure for Logic Speed and Memory Reliability
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Solution Overview
Problem
In the fabrication of embedded flash memory for automotive applications, there is a challenge in balancing the performance of logic CMOS transistors with the reliability of memory cells, as existing technologies struggle to integrate high-speed logic circuits with reliable memory storage effectively.
Innovation Solution
A semiconductor device with a substrate having both a flash memory region and a logic device region, featuring metal select gates with opposite sidewalls and polysilicon memory gates, along with oxide-nitride-oxide charge storage structures and high-k gate dielectric layers, is developed. The method involves forming metal gates and select gates with the same structure, including high-k gate dielectric layers and conductive electrodes, and integrating source/drain doping regions adjacent to the memory gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used to integrate flash memory with logic CMOS circuits, then manufacturing simplicity is maintained, but the balance between logic transistor performance and memory cell reliability deteriorates
Solution Approach 1:
The patent merges the fabrication processes for flash memory and logic CMOS circuits into a unified process flow. The metal gate formation, high-k dielectric deposition, and doping steps are combined to create both memory transistors and logic transistors simultaneously, reducing the number of separate fabrication stages while maintaining reliability improvements
Solution Approach 2:
The invention uses universal fabrication steps that serve dual purposes: the same metal gate deposition and high-k dielectric formation processes create structures that function both as memory cell components and logic transistor components. This multi-functional approach allows a single fabrication sequence to address both reliability requirements without adding separate process lines
2Speed
If high-speed logic CMOS circuits are integrated with flash memory for automotive applications, then data processing speed is improved, but the fabrication process becomes more complex to maintain both performance and reliability
Solution Approach 1:
The patent applies local quality by differentiating the gate structure characteristics in different regions: flash memory transistors receive specific doping profiles and gate material compositions optimized for memory operation, while logic CMOS transistors receive adjustments optimized for high-speed switching. This localized optimization allows high-speed performance in logic regions without compromising memory reliability, all within a unified fabrication process
3Reliability
If metal gates with high-k gate dielectric layers are used in flash memory transistors, then memory cell reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The invention employs parameter changes by systematically adjusting the deposition temperatures, thicknesses, and material compositions of the high-k gate dielectric layers and metal gates. By optimizing these parameters within the fabrication process, the patent achieves reliable memory cell operation with high-k dielectrics while maintaining manufacturability through controlled parameter variations rather than requiring extreme precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of embedded flash memory by ensuring consistent gate structures and charge storage, improving data processing speed and memory cell integrity, thereby addressing the balance between logic transistor performance and memory cell reliability.
Implementation Method 1
each of the metal gate and the metal select gate comprises a high-k gate dielectric layer and a conductive gate electrode
Implementation Method 2
each of the two charge storage structures comprises an oxide-nitride-oxide (ONO) storage structure
Data Source
AI summary
A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.