Programmable IC Interconnect Boundary Modeling for Multi-Die Variants
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost of manufacturing multiple integrated circuit (IC) variants with varying logic capacities is a challenge, as each variant requires a new mask set, which can be expensive, and existing methods do not efficiently manage localized defects or customer demand effectively.
Innovation Solution
A method involving a multi-product IC die that can be packaged to render certain portions non-operational, allowing for the creation of multiple IC variants from a single die, with configuration options controlled by a product selection code, enabling flexible production based on demand and defect management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a new mask set is created for each IC variant to meet different logic capacities, then product customization and customer demand alignment are improved, but manufacturing cost increases significantly
Solution Approach 1:
The IC die is divided into multiple functional portions with optional boundaries, allowing different combinations of portions to be activated or deactivated. This segmentation enables a single mask set to produce multiple IC variants by controlling which portions are operational, thereby reducing the need for separate mask sets for each variant.
Solution Approach 2:
The patent introduces dynamic configuration capabilities where portions of the IC can be selectively activated or deactivated based on the desired variant. This is achieved through configurable boundaries and optional portions that can be enabled or disabled without requiring physical changes to the die structure, allowing flexible adaptation to different customer demands.
2Reliability
If localized defects are discarded to maintain product quality, then reliability is improved, but productivity and resource utilization deteriorate
Solution Approach 1:
When localized defects are detected in a portion of the IC die, that specific defective portion is extracted or isolated from the functional portions. The defective area can be rendered non-operational while the remaining healthy portions continue to function, allowing the IC to be salvaged and reused rather than discarding the entire die.
Solution Approach 2:
The patent converts the presence of localized defects into a benefit by using them to define optional boundaries. Defective portions can be intentionally excluded from operational areas, and the boundaries are configured to avoid these regions. This approach transforms waste material into a design feature that maintains product reliability while maximizing resource utilization.
3Ease of manufacture
If multiple IC variants are produced from a single die, then manufacturing cost is reduced, but device complexity increases
Solution Approach 1:
The IC die is designed with universal functionality to support multiple variants through optional portions and configurable boundaries. A single die structure can be configured to produce different IC variants by selectively activating or deactivating portions, eliminating the need for separate dedicated dies for each variant and reducing manufacturing complexity despite the multi-functional design.
Data Source
AI summary
A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.