RRAM Top Electrode Blocking Layer for Leakage Prevention

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Solution Overview

Problem

During the manufacturing of resistive random access memory (RRAM) cells, leakage paths can form due to damage or contamination during the patterning process, particularly when forming sidewall spacers, which can lead to etch damage and affect the integrity of the RRAM cells.

Innovation Solution

A blocking layer is introduced over the RRAM stack, which is selectively etched to remain within recesses, protecting the cells from damage and allowing for the formation of sidewall spacers without interfering with the contact between the via and the top electrode, thereby preventing leakage paths and maintaining the structural integrity of the RRAM cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If sidewall spacers are formed during the patterning process, then the structural integrity of the RRAM cell is improved, but leakage paths can form due to damage or contamination

Engineering Contradiction:

Improvestructural integrityVSAvoidleakage prevention

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

A blocking layer is introduced as an intermediary component between the top electrode and the sidewall spacers. This blocking layer prevents direct contact and potential contamination between the electrode and spacer materials during the patterning process, thereby eliminating leakage paths while maintaining the structural integrity provided by the sidewall spacers.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a blocking layer is introduced to prevent leakage paths, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improveleakage preventionVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The blocking layer is designed with specific material properties and thickness parameters that enable it to perform its protective function while being compatible with existing manufacturing processes. By optimizing these parameters, the layer prevents leakage without requiring fundamental changes to the manufacturing workflow, thus limiting the increase in device complexity.

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If the blocking layer is selectively etched to remain within recesses, then manufacturing precision is improved, but the etch process complexity increases

Engineering Contradiction:

Improveblocking layer positioningVSAvoidetch process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The blocking layer is selectively etched to remain only within recesses of the top electrode surface, creating a non-uniform distribution pattern. This local presence strategy provides precise protection only where leakage paths are most likely to form, while simplifying the overall etch process by removing the blocking layer from other areas where it is not needed.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10862029B2Top electrode for device structures in interconnect

Publication Date: 2020.12.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.