Programmable Logic Block Slices With Two-Stage Routing Layout
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) have homogeneous programmable logic block architectures with limited slice types, leading to inefficient resource utilization, larger die sizes, and inadequate scalability, as well as non-optimized routing architectures that hinder performance and power efficiency.
Innovation Solution
The implementation of programmable logic devices with multiple logic block slices of different types within each programmable logic block, along with a two-stage routing circuit for efficient signal routing, allowing for optimized logic block architecture and reduced die size, and a flexible routing architecture that minimizes interconnect delay and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If homogeneous programmable logic blocks with limited slice types are used, then device complexity is reduced, but resource utilization efficiency deteriorates and die size increases
Solution Approach 1:
The patent implements heterogeneous logic block slices with different functionalities (combining LUTs, registers, and memory elements in varying configurations) within the same programmable logic block. This allows different regions of the PLB to have specialized structures optimized for specific functions, improving resource utilization without significantly increasing overall device complexity through systematic organization.
Solution Approach 2:
The programmable logic block is divided into multiple heterogeneous slices, each capable of independent configuration. This segmentation allows fine-grained resource allocation where each slice can be programmed for specific tasks, thereby improving resource utilization efficiency while maintaining manageable complexity through modular design.
2Speed
If conventional routing architecture optimized for per-LUT performance is used, then signal routing performance for individual LUTs is improved, but overall die area efficiency deteriorates and scalability is limited
Solution Approach 1:
The routing architecture implements multi-functional interconnect structures that can serve multiple logic block slices simultaneously. The shared routing resources provide flexible signal distribution to different slice types (LUTs, registers, memory) without requiring dedicated routing for each element, thereby improving die area efficiency while maintaining adequate routing performance through programmable routing controls.
Solution Approach 2:
The patent merges routing resources for different slice types into shared interconnect structures. Instead of having separate routing paths for LUTs, registers, and memory elements, the architecture combines these into unified routing fabric that can be dynamically configured, reducing overall routing area while providing flexible signal distribution to all logic elements.
3Ease of manufacture
If conventional homogeneous logic block architecture is used, then manufacturing and design simplicity is maintained, but scalability to higher density PLD sizes deteriorates
Solution Approach 1:
The patent employs parameterizable logic block configurations where the number, type, and arrangement of slices can be adjusted based on density requirements. By changing parameters such as slice count, slice type distribution, and routing resource allocation, the same basic architecture can be scaled to different PLD densities while maintaining design simplicity through consistent structural patterns.
Solution Approach 2:
The architecture implements dynamic configurability where logic block slices can be programmed to assume different functional roles based on application requirements. This dynamic adaptation allows the same physical structure to serve multiple purposes across different density implementations, enhancing scalability without requiring fundamentally different designs for each density level.
Data Source
AI summary
Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.