Four-Layer SCR Structure for Higher ESD Holding Voltage
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Solution Overview
Problem
Silicon-controlled rectifiers (SCRs) have a low holding voltage, making them unsuitable for high-voltage applications due to the risk of unintended electrostatic discharge (ESD) triggering, which can cause electrical disturbances or damage, and increasing the holding voltage through series arrangement is not feasible due to substrate parasitics and high costs of fully isolated device technologies.
Innovation Solution
A four-layer semiconductor device with epitaxial layers and electrical insulation that reduces the current gain product of bipolar transistors, increasing the holding voltage by expanding the effective base length of the transistors and using multiple insulations to force current flow through the semiconductor substrate, thereby enhancing the operational voltage beyond the typical limits of standard SCRs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the holding voltage is increased by arranging several SCRs in series, then the holding voltage increases above the operational voltage, but the device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent segments the base region of the bipolar transistor by introducing an electrical insulation layer that divides the base into two separate regions. This segmentation increases the effective base length without requiring multiple SCR devices in series, thereby increasing holding voltage while maintaining single-device simplicity
Solution Approach 2:
The patent extends the base length in the vertical dimension by having the electrical insulation layer extend from the epitaxial layer into the semiconductor substrate. This dimensional extension achieves increased holding voltage without adding horizontal complexity through series arrangements
2Reliability
If fully isolated device technologies such as Silicon-on-Insulator are used to increase holding voltage, then the holding voltage increases by simple device stacking, but the material cost and investment increase due to silicon real estate requirements
Solution Approach 1:
The patent applies electrical insulation locally only in the region where base length extension is needed, rather than using global isolation techniques like Silicon-on-Insulator. This localized approach reduces material costs and silicon real estate requirements while achieving the desired holding voltage increase
Solution Approach 2:
The patent introduces an electrical insulation layer as an intermediary element within the semiconductor structure that provides the necessary isolation and base length extension without requiring expensive fully isolated device technologies
3Adaptability or versatility
If the operational voltage exceeds the holding voltage by far, then high voltage products can operate at higher voltages, but the risk of unintended ESD triggering and latch-up increases
Solution Approach 1:
The patent changes the critical parameter of holding voltage by extending the effective base length through electrical insulation. This parameter change ensures that holding voltage exceeds operational voltage, eliminating the risk of unintended ESD triggering while maintaining broad operational voltage range
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the holding voltage beyond the typical limits of standard SCRs, reducing the risk of unintended ESD triggering and enabling the use of SCRs in high-voltage applications without the need for costly fully isolated device technologies, while maintaining a low doping concentration for efficient operation.
Implementation Method 1
an electrical insulation extending at least partially inside the epitaxial layer and that prevents a current from flowing between the first device terminal and the second device terminal that does not at least partially flow through the semiconductor substrate
Implementation Method 2
two bipolar transistors are formed. A first bipolar transistor is formed using the first contact region, which is of the first charge type, the first region, which is of the second charge type, and the semiconductor substrate, which is of the first charge type
Data Source
AI summary
The present disclosure generally relates to a four-layer semiconductor device, such as a silicon-controlled rectifier. Further aspects of the present disclosure relate to an electrostatic discharge (ESD), protection circuit including the same. In the four-layer semiconductor device in accordance with the present disclosure, an electrical insulation is provided that extends at least partially inside the epitaxial layer and that prevents a current from flowing between the first device terminal and the second device terminal that does not at least partially flow through the semiconductor substrate.