Power Semiconductor Layout With Variable Spacing for Thermal Crowding
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Solution Overview
Problem
High power semiconductor devices face challenges with thermal crowding, leading to inefficient use of active device area and reduced power capability due to thermal gradients, especially in densely packed modules with wide bandgap semiconductor materials like GaN and SiC.
Innovation Solution
The arrangement of power semiconductor devices with variable spacing and offset distances within a module to reduce thermal crowding, allowing for increased density and improved thermal profiles, thereby enhancing power capability and operating lifetimes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple power semiconductor devices are densely packed in a power module, then the power density and device area utilization are improved, but thermal crowding occurs leading to thermal gradients and reduced power capability
Solution Approach 1:
The patent applies local quality by implementing variable spacing between power semiconductor devices based on their specific locations within the module. Devices in central positions have larger spacing to accommodate heat accumulation, while peripheral devices have smaller spacing. This non-uniform spacing strategy optimizes thermal management locally while maintaining high overall device density.
Solution Approach 2:
The patent employs asymmetry by deliberately creating non-uniform spacing patterns between devices rather than using uniform spacing. The spacing is asymmetrically distributed with larger gaps in thermally critical central regions and smaller gaps in peripheral regions, breaking the symmetry to achieve better thermal balance across the module.
2Ease of manufacture
If uniform spacing is used between power semiconductor devices, then manufacturing simplicity is maintained, but thermal balancing is insufficient leading to reduced operating lifetime
Solution Approach 1:
The patent transitions from uniform to non-uniform spacing with locally optimized distances between devices. The spacing is specifically adjusted based on thermal considerations for each device position, with central devices having larger spacing to reduce thermal crowding and improve heat dissipation, thereby enhancing reliability without significantly complicating manufacturing.
3Temperature
If larger spacing is provided between power semiconductor devices, then thermal crowding is reduced and thermal balancing is improved, but the active device area utilization decreases
Solution Approach 1:
The patent implements local quality through position-dependent spacing where the distance between adjacent devices varies based on their location. Peripheral devices maintain smaller spacing to maximize area utilization, while central devices have larger spacing to improve thermal balance. This localized optimization achieves both goals simultaneously.
Solution Approach 2:
The patent addresses the spacing-thermal balance tradeoff by introducing offset distances in addition to spacing variations. Devices are positioned with both longitudinal spacing and transverse offsets, utilizing two-dimensional positioning to achieve optimal thermal balance while maintaining high area utilization that would be impossible with unidirectional spacing adjustments alone.
Data Source
AI summary
Power semiconductor devices, and more particularly arrangements of power semiconductor devices for improved thermal performance in high power applications are disclosed. Arrangements for multiple power semiconductor devices within a package and/or module are provided that more efficiently utilize the active device area of each power semiconductor device for a given operational specification. Certain arrangements are provided that reduce the effects of thermal crowding in order to provide increased power capability or a similar power capability in a reduced device size. Improved thermal balancing may be provided by variable spacing and/or variable offset distances between next-adjacent power semiconductor devices. In this manner, active areas of power devices and/or modules may include an increased density of power semiconductor devices within a given area while also exhibiting improved thermal profiles during operation, thereby providing improved operating characteristics and/or increased operating lifetimes.