Semiconductor Integrated Circuit Test Signal Bypass
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Solution Overview
Problem
The design of semiconductor integrated circuit devices faces challenges in testing large-scale integrated circuits due to clock phase differences between flip-flops during test scanning, which complicates timing design and adjustment, and existing methods are inadequate for facilitating circuit design and testing efficiency, especially when using multiple IPs.
Innovation Solution
A semiconductor integrated circuit device is designed with a driving unit, a switch, and a transmission unit that allows external test signals to bypass the normal clock signal path, enabling independent timing adjustment and phase synchronization of test signals across different circuits, reducing the need for precise timing design and allowing for easier evaluation and adjustment of local circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test scanning is performed using known testing methods for large integrated circuits, then testing can be executed, but clock phase differences occur between flip-flops which exceeds allowable values and makes precise testing difficult
Solution Approach 1:
The invention divides the clock signal distribution into multiple independent paths: one path for normal operation and another path for test scanning. Each path can be independently controlled and adjusted, allowing the test clock signal to be supplied separately to different circuit blocks without being constrained by the phase differences that occur in the normal single-path distribution system.
Solution Approach 2:
The invention introduces a clock signal distribution unit as an intermediary component that receives a single clock signal and generates multiple test clock signals with adjustable phases. This intermediary unit acts as a mediator between the clock source and the flip-flops, enabling precise phase adjustment to compensate for path delay differences and achieve synchronized timing across all circuit blocks during test scanning.
2Reliability
If timing design is performed considering phase difference for test operation, then testing can be executed, but circuit design becomes difficult and complex
Solution Approach 1:
The clock signal distribution unit automatically performs phase adjustment and synchronization based on detected path delay differences. The system self-regulates by measuring the actual timing differences in each distribution path and automatically generating compensating phase shifts, eliminating the need for manual timing design calculations and complex external adjustment procedures.
Solution Approach 2:
The invention implements a feedback mechanism where the clock signal distribution unit continuously monitors the phase relationships and timing differences in the clock distribution paths. Based on this feedback information, the unit dynamically adjusts the phase of test clock signals to maintain synchronized timing across all circuit blocks, simplifying the design process by making the system self-adjusting rather than requiring pre-calculated fixed timing parameters.
3Device complexity
If a single line for supplying clock signal is used, then circuit structure is simple, but it does not allow selecting and activating a local portion for evaluation and adjustment
Solution Approach 1:
The clock signal distribution system is segmented into multiple independent output paths, each capable of being individually activated or deactivated. This segmentation allows the test system to select and activate only the specific local circuit portions that need to be evaluated, rather than requiring the entire circuit to be activated through a single distribution line.
Solution Approach 2:
The clock signal distribution unit is designed to be dynamically reconfigurable, allowing the selection of which circuit blocks receive clock signals during test scanning. The system can dynamically switch between different distribution patterns and activate specific local portions as needed, providing versatility in circuit evaluation while maintaining a relatively simple overall structure.
Data Source
AI summary
It is provided a semiconductor integrated circuit device capable of easily designing a large scale circuit, particularly a circuit of a system LSI designed by combining circuits using plural intellectual properties and the like. The semiconductor integrated circuit includes a driving unit which is connected to a driven circuit via a transmission line and supplies a driving signal for driving the driven circuit to the driven circuit, a switch which is inserted into the transmission line between the driven circuit and the driving unit and which causes the driving signal, which is to be supplied to the driven circuit, to flow or to be cut off, and a transmission unit which is connected to the transmission line between the switch and the driving unit, and which transmits, to the driven circuit, a test signal supplied from outside the semiconductor integrated circuit device instead of the driving signal.