Inverting FPGA Flip-Flop for Faster Routed Data Paths
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Solution Overview
Problem
FPGA designs face limitations in packing efficiency and performance due to the long series connection of multiplexers required for signal routing, leading to significant performance degradation, especially when using CMOS buffers which introduce unacceptable delays.
Innovation Solution
The introduction of an inverting flip-flop with a tri-state inverter breaks the long chain of pass transistors, acting as a buffer while inverting the logical polarity, thus reducing signal propagation delay to that of a single gain stage, and requiring design software compensation for logic inversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a long series connection of multiplexers is used for signal routing in FPGA, then routing flexibility is improved, but signal propagation delay increases significantly
Solution Approach 1:
The patent introduces tri-state buffers as intermediary elements between multiplexers in the routing path. These buffers act as mediators that restore signal strength and reduce propagation delay without compromising routing flexibility, effectively breaking the long series connection of multiplexers into shorter segments with buffer insertion points.
Solution Approach 2:
The routing architecture is segmented by inserting tri-state buffers at strategic points within the multiplexer chain. This segmentation divides the long series connection into multiple shorter stages, with each stage having reduced propagation delay, while the overall routing flexibility is maintained through the programmable nature of the segmented architecture.
2Speed
If CMOS buffers are used to reduce signal propagation delay, then signal speed is improved, but additional delay is introduced due to buffer switching characteristics
Solution Approach 1:
The patent employs tri-state buffers with inverted control logic compared to conventional CMOS buffers. By inverting the enable signal polarity and using complementary control schemes, the buffer switching delay is minimized and the effective signal propagation speed is improved, counteracting the typical delay penalty associated with buffer insertion.
3Productivity
If more logic modules and routing resources are packed into the FPGA array, then functionality is improved, but signal propagation delay increases due to longer routing paths
Solution Approach 1:
Tri-state buffers are strategically positioned as intermediary elements within the packed logic module array, serving as local signal restoration points that reduce the effective propagation delay across densely packed routing resources while maintaining high functionality density.
Solution Approach 2:
The patent introduces a temporal dimension to the routing architecture by using clocked tri-state buffers that can be dynamically enabled or disabled. This allows the routing fabric to be reconfigured in time domains, effectively managing signal propagation delays in densely packed FPGAs without sacrificing functionality.
Data Source
AI summary
A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.