Four-Layer SCR Isolation Structure for Higher ESD Holding Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Silicon-controlled rectifiers (SCRs) have a low holding voltage, making them unsuitable for high-voltage applications due to the risk of unintended electrostatic discharge (ESD) triggering, which can cause electrical disturbances or damage, and increasing the holding voltage through series arrangement is not feasible due to substrate parasitics, especially in high-voltage products.
Innovation Solution
A four-layer semiconductor device with epitaxial layers and electrical insulation that reduces the current gain product of bipolar transistors, thereby increasing the holding voltage beyond typical operational limits, using a combination of deep trench isolation and buried implants to adjust breakdown and triggering voltages, and allowing for bi-directional operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the holding voltage is increased to above operational voltage levels, then the risk of unintended ESD triggering is reduced, but the device becomes unsuitable for high voltage applications
Solution Approach 1:
The device is divided into multiple SCR units connected in series, each contributing to the overall holding voltage. This segmentation allows the total holding voltage to be distributed across several devices, enabling the system to achieve high holding voltage suitable for high voltage applications while maintaining reliability.
2Reliability
If several SCRs are arranged in series to increase holding voltage, then the holding voltage increases above operational voltage, but substrate parasitics make this method infeasible for high voltage products
Solution Approach 1:
An intermediate n-type region is introduced between the PNP and NPN transistors to act as a mediator. This intermediate region provides a controlled current path that bypasses the substrate parasitics, allowing the series connection of SCRs to achieve high holding voltage without being limited by substrate parasitic effects.
3Reliability
If fully isolated device technologies such as Silicon-on-Insulator are used to increase holding voltage, then the holding voltage increases through simple device stacking, but high investment is required due to silicon real estate and material costs
Solution Approach 1:
The invention changes the doping parameters and structural configuration of the semiconductor device to achieve high holding voltage using standard silicon technology. By adjusting the doping concentrations and introducing the intermediate n-type region, the device achieves high holding voltage without requiring expensive Silicon-on-Insulator technology, thereby reducing manufacturing investment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the holding voltage of the four-layer semiconductor device beyond standard limits, reducing the risk of unintended ESD triggering and enabling reliable operation in high-voltage environments while maintaining efficient current flow.
Implementation Method 1
an electrical insulation extending at least partially inside the epitaxial layer and that prevents a current from flowing between the first device terminal and the second device terminal that does not at least partially flow through the semiconductor substrate
Implementation Method 2
two bipolar transistors are formed. A first bipolar transistor is formed using the first contact region, which is of the first charge type, the first region, which is of the second charge type, and the semiconductor substrate, which is of the first charge type
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Aspects of the present disclosure generally relate to a four-layer semiconductor device, such as a silicon-controlled rectifier. Further aspects of the present disclosure relate to an electrostatic discharge, ESD, protection circuit comprising the same. In the four-layer semiconductor device in accordance with the present disclosure, an electrical insulation is provided that extends at least partially inside the epitaxial layer and that prevents a current from flowing between the first device terminal and the second device terminal that does not at least partially flow through the semiconductor substrate.