Smartcard Local Clock Recovery Using Open-Loop Fractional Delay
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Solution Overview
Problem
Existing clock generation circuits in portable devices, such as smartcards, face challenges in achieving low jitter and minimizing power consumption, especially in full-speed USB standards, where high frequency and multiple phases lead to increased power consumption.
Innovation Solution
The introduction of an additional delay in the open-loop clock recovery circuit allows for higher precision in clock recovery, with the delay being shorter than the Step of Time, enabling more granular control and reducing jitter, while also optimizing power consumption through calibration of the delay as a function of the Step of Time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a very high frequency oscillator with a high number of phases is used to achieve low jitter (±1.5 ns), then the jitter precision is improved, but the power consumption increases significantly
Solution Approach 1:
The clock generation function is segmented into two independent parts: a low-frequency reference oscillator (e.g., 32.768 kHz) and a separate delay line network. The delay line is segmented into multiple controllable delay elements that can be individually adjusted to achieve the required ±1.5 ns jitter precision without requiring a high-frequency oscillator, thus avoiding the power consumption penalty.
Solution Approach 2:
The invention changes the operating parameters by using a low-frequency oscillator combined with a variable delay line instead of a high-frequency oscillator. The delay line parameters (delay amount) are dynamically adjusted to compensate for frequency variations and achieve the required timing precision, effectively decoupling jitter performance from oscillator frequency and power consumption.
2Measurement precision
If the Step of Time is reduced to achieve higher clock recovery precision, then the jitter tolerance is improved, but the oscillator frequency must be increased which raises power consumption
Solution Approach 1:
The timing measurement function is segmented by introducing a separate delay line that can be independently adjusted. Instead of reducing the oscillator Step of Time, the invention adds a variable delay element that provides fine-grained timing adjustment, allowing precise clock recovery without increasing oscillator frequency or power consumption.
Solution Approach 2:
A variable delay line is introduced as an intermediary element between the low-frequency oscillator and the clock recovery circuit. This intermediary component provides the necessary timing precision by introducing adjustable delay, effectively mediating between the low-power oscillator and the high-precision timing requirement without requiring high oscillator frequency.
Data Source
AI summary
One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal φ(0) to φ(2i−1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal φ(0) to j(2i−1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal φ(0) to φ(2i−1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.