3D Memory Cell Programming Order to Reduce Disturbance
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Solution Overview
Problem
In three-dimensional semiconductor memory devices, the variation in channel hole sizes due to etching processes leads to differences in program speed among memory cells, causing program disturbances when cells with smaller channel holes are programmed before those with larger holes, as the electric field is stronger at smaller cells, leading to faster programming and potential interference with previously programmed cells.
Innovation Solution
A method and device that initialize the channel of memory cells based on their size, starting with cells having larger channel holes to reduce program disturbances by controlling the program order and voltage application, using an address scramble scheme that prioritizes programming cells with slower program speeds first, and employing incremental step pulse programming to manage voltage and reduce interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells with smaller channel holes are programmed first, then program speed is improved, but program disturbance increases due to stronger electric field affecting previously programmed cells
Solution Approach 1:
The patent inverts the conventional programming order by programming memory cells with larger channel holes first, then programming cells with smaller channel holes. This reversal prevents program disturbance because the stronger electric field from smaller cells does not interfere with already programmed larger cells, as the programming direction is reversed from the traditional approach
Solution Approach 2:
The patent applies preliminary channel initialization before programming operations. The channel is initialized in advance to a specific voltage level, ensuring that when programming begins with larger channel holes, the electric field distribution is controlled and prevents unwanted charge injection into unselected cells, thereby reducing program disturbance
2Quantity of substance
If three-dimensional stacked memory cells are used to improve integration density, then degree of integration is improved, but program disturbance increases due to variation in channel hole sizes
Solution Approach 1:
The patent applies different programming strategies to different regions of the three-dimensional memory structure. Memory cells at different vertical positions and with different channel hole sizes are programmed in a specific sequence that accounts for their local characteristics. The channel initialization voltage and programming pulses are tailored to the specific cell being programmed, ensuring uniform programming results across the three-dimensional structure without causing program disturbance
Solution Approach 2:
In the three-dimensional stacked structure, the patent reverses the programming sequence from conventional approaches by programming cells with larger channel holes (typically at certain vertical positions) before programming cells with smaller channel holes. This inversion compensates for the etching-induced size variations and prevents program disturbance in the high-density three-dimensional configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces program disturbances by ensuring cells with larger channel holes are programmed first, minimizing the accumulation of charges and reducing the impact on unselected memory cells, thereby improving the reliability and efficiency of programming in three-dimensional memory devices.
Implementation Method 1
initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure
Implementation Method 2
a memory cell, the diameter of which is relatively small, may be first programmed
Data Source
AI summary
A three-dimensional (3D) nonvolatile memory device includes a cell string. The cell string includes a pillar structure comprising a ground selection transistor, a plurality of memory cells, and a string selection transistor stacked vertically over a substrate. The memory cells comprise a first cell group and a second cell group stacked on the first cell group, and a horizontal width of at least a portion of the pillar structure decreases in a depth direction towards the substrate. A method of programming the memory device includes initializing a channel of a memory cell of the first cell group of the cell string through the ground selection transistor of the pillar structure, and then applying a program voltage to the memory cell of the pillar structure of the cell string.