Read-Only Memories TRIZ Cases

A dummy word line applies an intermediate voltage to isolate unselected cells in NAND flash memory arrays.

A multi-level storage algorithm determines desired characteristic states and successively stores equivalent states in memory cells to reduce distribution overlap.

Adjusting read pass voltages on neighbor word lines during internal data load operations to preserve lower page data integrity.

A multi-level memory cell programming method uses auxiliary latches to transfer values between MSB and LSB nodes during write operations.

A memory controller measures error bits across word lines to identify groups exceeding thresholds and selects specific program operation parameters.

A storage controller adjusts erase voltage levels based on cumulative wear to optimize nonvolatile memory block operations.

Adjusting recovery voltage via targeted word line biases reduces peak current consumption and improves programming efficiency in non-volatile memory devices.

A common control circuit manages concurrent read operations across independent memory planes to enable early data output from single-bit cells.

Applying a positive well voltage after the word line reaches a target negative level prevents premature capacitive coupling during non-volatile memory erasing.

Shared programming devices and integrated diodes manage current paths in fuse-based memory circuits, reducing area by 40% while maintaining data accuracy.

Segmenting the single store transistor into two independent units doubles programming speed and cycle durability while widening the read current margin.

Segmented voltage sources powered by current sensing feedback reduce consumption in mixed voltage non-volatile memory integrated circuits.

Modified Vpass voltage biases unselected word lines to mimic programmed cell drain resistance, tightening the voltage threshold window from 200 mV to ±100 mV.

A page buffer circuit uses a single latch to store program, verify, and preparation data across multi-phase operations.

Segmented discharge paths and staged control logic extend effective supply voltage range to mitigate data corruption from RC effects.

A fully depleted silicon-on-insulator flash memory design partitions the chip into distinct bulk and FDSOI regions to minimize leakage current.

Segmented source lines receive intermediate voltage levels to reduce stress on half-selected bitcells and prevent write disturbance errors.

A phase change memory reading circuit uses a shift current to charge or discharge a bit line before voltage comparison.

A word line enable method uses stepwise voltage increases to control signal lines in flash memory devices.

A ROM computing unit performs in-memory matrix operations using adjustable electrical elements to store weights and compute results directly within the memory array.

A memory circuit uses differential sense amplifiers to compare adjacent cell currents for data retrieval.

Integrated trace module generates and stores diagnostic data within non-volatile memory, eliminating external connection requirements.

A non-volatile memory controller implements a coarse write process that identifies less responsive storage cells early to provide additional charge.

Homogeneous control cells mimic normal memory operations to detect programming or erasure failures.

Two-step channel precharge manages word line biases to prevent program disturbance in nonvolatile memory devices operating at reduced power supply voltages.

Negative bit line biasing during programming improves connection consistency and reduces power consumption by lowering turn-on voltage requirements.

Alternating write logical state steps reduces interference on unselected memory cells, maintaining data integrity in high-density arrays.

Drive control signals disable inactive chip power circuits during non-active intervals, reducing unnecessary current consumption.

Programming larger channel holes first in a 3D memory structure reduces program disturbance by preventing interference from stronger fields at smaller cells.

Segmented sub-blocks with independent switching transistors maintain block yield and reduce disturb effects during programming.

Segmented bit lines decouple charge coupling during programming, eliminating corrective operations and maintaining threshold voltage stability.

A flash memory controller executes staged erase operations across multiple blocks to reduce total processing time.

A read voltage setting method adjusts test voltages to minimize error bits in rewritable non-volatile memory cells.

A memory controller applies distinct verify voltages to different word lines based on their physical location.

Adjusts read levels based on programming status to compensate for voltage shifts in partially programmed blocks.

A nonvolatile memory device uses a control logic circuit to perform first and second sensing schemes on setting data stored in a page buffer.

A write cycle recording device tracks writing loop counts for non-volatile memory blocks using a dedicated storage component and controller.

A memory device adjusts channel initialization periods based on read modes to remove hot holes from semiconductor channels.

A divisional program control circuit segments programming operations into multiple cycles to manage memory cell writes.

Protruding interlayer insulating layers define lateral grooves with decreasing width, preventing charge movement between adjacent storage patterns.

Dual-voltage sensing reads drain currents at distinct gate potentials to identify breakdown states in OTP memory cells.

Sequential programming staggers subgroup activation to minimize power noise and bit line leakage during flash memory operations.

A storage-computation integrated indexing system uses cross-point arrays for parallel data comparison.

A string selecting control voltage generator adjusts output levels based on ambient temperature to maintain adequate programming windows.

A semiconductor memory device integrates DRAM cells with e-fuses to store and refresh repair information during operation.

Floating unselected partial SGD transistors and reducing adjacent cell voltage via capacitance coupling to manage electrical states.

Differentiated pass voltages applied to adjacent word lines reduce electrical coupling and maintain stable threshold voltage distributions.

Varying programming pulse duration between verification operations maintains effective cell programming when maximum voltage limits are reached.

A flash memory control logic unit adjusts read threshold voltage levels to compensate for coupling effects between adjacent cells.