OTP Memory Cell Programming via Negative Bit Line Bias
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Solution Overview
Problem
Existing one-time programmable (OTP) semiconductor devices face variability in programmed connection quality due to inconsistent gate oxide breakdown, leading to high turn-on voltage requirements and power consumption, which is suboptimal for low-power applications.
Innovation Solution
A method involving setting a negative voltage on the bit line during programming, along with positive voltages on the gate electrodes, to rupture the oxide layer and improve the consistency and efficiency of programming in OTP memory cells, reducing channel resistance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate oxide breakdown programming is used, then programming can be achieved, but programmed connection quality varies and turn-on voltage is high
Solution Approach 1:
The patent changes the voltage parameters during programming by applying a negative voltage to the bit line while applying positive voltages to the gate electrodes. This parameter change in the programming process modifies the electric field distribution and enables more consistent gate oxide breakdown, resulting in uniform programmed connection quality across all memory cells in the array.
2Reliability
If high turn-on voltage is used to ensure programming, then programming reliability improves, but power consumption increases
Solution Approach 1:
The patent employs negative voltage on the bit line during programming, which changes the voltage parameters to enable lower turn-on voltage operation. This parameter modification maintains programming reliability while significantly reducing the voltage required for read operations, thereby lowering power consumption.
Solution Approach 2:
The patent replaces the conventional positive voltage biasing mechanism with a negative voltage biasing mechanism on the bit line. This substitution fundamentally changes how the gate oxide breakdown is induced, enabling more efficient programming with lower voltage requirements and reduced power consumption while maintaining reliable programmed connections.
3Productivity
If conventional programming method is used, then memory cells can be programmed, but read voltage is high and power consumption is high
Solution Approach 1:
The patent modifies the voltage parameters by applying negative voltage to the bit line during programming, which creates more favorable electric field conditions. This parameter change enables the memory cells to operate at lower read voltages afterward, significantly reducing read power consumption while maintaining good programming efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more consistent programming, lower read voltages, and significantly reduced power consumption, potentially achieving up to 10 times less power usage compared to conventional methods, while maintaining or improving programmed cell current.
Implementation Method 1
Programming is performed by the breakdown or rupture of the gate oxide 18 of the programming element, the second transistor. With the breakdown of the gate oxide 18, a conducting plug is formed through the gate oxide 18
Data Source
AI summary
A method of programming one-time programmable (OTP) memory cells in an array is described. Each memory cell has a MOSFET programming element and a MOSFET pass transistor, the MOSFET pass transistor having a gate electrode over a channel region between two source/drain regions, and the MOSFET programming element having a gate electrode over a channel region contiguous to a source/drain region either part of, or connected to, one of the two source/drains associated with the MOSFET pass transistor. The other source/drain region of the MOSFET pass transistor is coupled to a bit line. The memory cell is programmed by setting a first voltage of a first polarity on the gate electrode of the pass transistor to electrically connect the source/drain regions of the pass transistor; setting a second voltage of the first polarity on the gate electrode of the programming element; and setting a third voltage of a second polarity on the bit line. The voltage across an oxide layer between the gate electrode and channel region of the programming element ruptures the oxide layer and effectively programs the programming element.