Non-Volatile Memory Write Process Early Cell Verification
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Solution Overview
Problem
Traditional write processes for non-volatile memory devices, such as NAND flash memory, are inefficient due to the need for repeated charge pulses and verify operations, which are dictated by the slowest cells, leading to prolonged write times as the process waits for all cells to reach their threshold, especially in multi-level cell (MLC) storage systems.
Innovation Solution
The improved coarse phase write process identifies slower cells early and provides them with additional charge, reducing the number of pulses and verify operations, allowing the write process to proceed with fewer iterations and narrower charge distributions, thereby accelerating the write process by focusing on compensating slower cells rather than inhibiting faster ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional write processes use repeated charge pulses and verify operations to ensure all cells reach threshold, then write reliability is improved, but write time increases significantly
Solution Approach 1:
The patent performs a preliminary verify operation early in the coarse phase to identify slower cells before the main write process completes. This allows the system to pre-compensate for slow cells by providing additional charge pulses specifically to them, rather than waiting for all cells to naturally reach threshold through repeated full-array pulses.
Solution Approach 2:
The patent applies different charge pulse strategies to different cells based on their identified responsiveness. Faster cells receive standard pulse sequences while slower cells receive additional compensatory pulses. This localized differentiation allows the system to optimize write speed without sacrificing reliability, as each cell receives the precise amount of charge needed.
2Manufacturing precision
If the write process waits for all cells to reach threshold before proceeding, then charge distribution uniformity is improved, but productivity decreases
Solution Approach 1:
The system performs a preliminary identification of slow cells during an early verify operation and stores this information. This preliminary action allows the main write process to proceed at full speed while selectively compensating for slow cells through targeted additional pulses, rather than uniformly waiting for all cells to reach threshold.
Solution Approach 2:
The patent changes the charge pulse parameters dynamically based on cell responsiveness. After identifying slow cells, the system adjusts the number and timing of charge pulses specifically for those cells, increasing their charge delivery parameters while maintaining standard parameters for faster cells. This parameter adaptation achieves uniform charge distribution without uniform waiting time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the overall write time by narrowing the charge distributions and eliminating the need for extensive iterations, as slower cells receive extra charge to match the average charge levels, thus streamlining both the coarse and fine phases of the write process.
Implementation Method 1
The individual storage cells of a NAND flash memory, by contrast, are able to store more than two voltage levels. As such, NAND flash memory cells are able to store more than two logic states per storage cell.
Implementation Method 2
perform a verify operation to identify less responsive storage cells and provide additional charge to the less responsive storage cells
Data Source
AI summary
An apparatus is described. The apparatus includes a non volatile memory device that includes a controller to implement a coarse write process for the non volatile memory device. The non volatile memory device includes storage cells to store more than two logic states, wherein, the coarse write process is to perform a verify operation early in the coarse write process to identify less responsive storage cells and provide additional charge to the less responsive storage cells as compared to non less responsive storage cells that are to be programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write process.