Memory Controller Verify Voltage Adjustment
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Solution Overview
Problem
Memory systems face challenges in increasing writing speed while minimizing error bits during reading, as large increments in programming voltage lead to wider threshold voltage distributions and increased error bits, especially due to variations in data writing ease across different word lines.
Innovation Solution
The memory system adjusts verify voltages for each word line based on physical location and characteristics, using different adjustment values to optimize verify voltage levels, thereby reducing the width of threshold voltage distributions and minimizing error bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large increment in programming voltage is applied to increase writing speed, then writing speed is improved, but threshold voltage distribution width increases and error bits increase
Solution Approach 1:
The patent applies different verify voltage adjustment values to different word lines based on their physical locations. Word lines are divided into multiple regions (e.g., first region with larger adjustment value, second region with smaller adjustment value) to account for location-dependent variations in threshold voltage characteristics. This local differentiation allows optimized verification for each region while maintaining overall system reliability.
Solution Approach 2:
The patent changes the verify voltage parameter dynamically by applying different adjustment values depending on the word line region. The verify voltage is adjusted relative to the read voltage based on the specific region being accessed, allowing the system to adapt verification conditions to local threshold voltage distribution characteristics and minimize errors caused by large programming voltage increments.
2Reliability
If verify voltage is increased to reduce error bits, then reading accuracy is improved, but writing speed decreases due to more conservative programming
Solution Approach 1:
Different verify voltage adjustment values are applied to different word line regions based on their specific characteristics. Regions with higher susceptibility to errors receive larger adjustment values for enhanced verification, while regions with better characteristics use smaller adjustments, maintaining writing speed without compromising overall reading accuracy.
Solution Approach 2:
The patent applies verify voltage adjustments selectively rather than uniformly across all word lines. By applying larger adjustments only to specific regions where needed and smaller adjustments to other regions, the system achieves sufficient reading accuracy without the performance penalty of uniformly conservative programming across the entire memory array.
3Device complexity
If uniform verify voltage is applied to all word lines, then device complexity is reduced, but manufacturing precision deteriorates due to ignoring word line variations
Solution Approach 1:
The patent implements location-dependent verify voltage adjustment by dividing word lines into multiple regions and applying different adjustment values to each region. This approach accounts for physical variations in threshold voltage characteristics across different word line locations, improving manufacturing precision without requiring complex individual control for each word line.
Solution Approach 2:
The memory array's word lines are segmented into multiple regions (e.g., first region, second region) with distinct verify voltage adjustment characteristics. This segmentation allows the system to handle word line variations in a structured manner, improving precision by treating different regions differently while maintaining manageable system complexity through regional grouping rather than individual word line control.
Data Source
AI summary
According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.