Flash Memory Programming via Bit Line Segmentation
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Solution Overview
Problem
Flash memory devices experience unintended program operations due to charge coupling between adjacent memory cells, leading to threshold voltage changes and program disturb, requiring additional operations to correct threshold voltage distribution.
Innovation Solution
A flash memory device and method that simultaneously programs adjacent memory cells using a page buffer circuit with latches and a select circuit to electrically couple bit lines, reducing charge coupling by activating only one side of the adjacent memory cells during programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a high voltage is applied to program the selected memory cell, then the threshold voltage of the selected memory cell increases to a higher level, but the threshold voltage of adjacent unselected memory cells also increases due to charge coupling, causing accidental programming
Solution Approach 1:
The bit lines are divided into first bit lines and second bit lines, with adjacent bit lines being electrically decoupled during programming. This segmentation isolates the selected memory cell from adjacent cells, preventing charge coupling while maintaining programming accuracy.
Solution Approach 2:
A select circuit is introduced as an intermediary component between the bit lines and memory cells. This select circuit controls the electrical coupling between bit lines and memory cells, enabling selective programming while blocking charge coupling to adjacent cells.
2Manufacturing precision
If additional programming operations are performed to correct threshold voltage distribution, then programming accuracy is improved, but programming time increases
Solution Approach 1:
Adjacent bit lines are electrically decoupled before the programming operation begins. This preliminary action prevents charge coupling from occurring in the first place, eliminating the need for subsequent corrective programming operations and reducing total programming time.
3Productivity
If adjacent memory cells are programmed simultaneously, then programming speed is improved, but charge coupling between adjacent cells causes threshold voltage changes
Solution Approach 1:
The bit line structure is segmented into first bit lines and second bit lines that are electrically decoupled during simultaneous programming. This allows multiple memory cells to be programmed in parallel (improving speed) while the decoupling prevents charge coupling between adjacent cells (maintaining threshold voltage stability).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces threshold voltage changes in adjacent memory cells, eliminating the need for additional programming operations and maintaining accurate programming without additional circuits, thus enhancing programming speed and control.
Implementation Method 1
a parasitic capacitance Cx may be disposed between the adjacent floating gates 41, 51, and 61. Therefore, when the program voltage is applied to the selected word line WL30>, charge coupling between the selected memory cell 50 and unselected memory cells 40 and 60 occurs due to the parasitic capacitance Cx
Data Source
AI summary
A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.