Flash Memory Block Erase Pipeline and Staged Controller
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Solution Overview
Problem
The erase operation in flash memory devices is lengthy and power-consuming, leading to performance deterioration and potential misjudgment as a malfunctioned device, especially as the number of cells in a block increases, necessitating a method to quickly generate free blocks.
Innovation Solution
A pipeline configuration and erase method that divides the erase operation into multiple stages, allowing for simultaneous partial or subblock erase operations across multiple blocks, utilizing a controller to manage first and second stage erase operations in distinct time intervals, thereby reducing the overall erase time and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the erase operation is performed on a block with increasing number of cells, then the storage capacity is improved, but the erase time period becomes longer
Solution Approach 1:
The erase operation is divided into multiple stages (first stage erase operation and second stage erase operation) that are performed sequentially on different blocks in a pipeline fashion. This segmentation allows the system to process multiple blocks concurrently at different stages, reducing the overall time required to erase all blocks while maintaining the ability to handle large numbers of cells.
2Quantity of substance
If the erase operation is performed on a block with increasing number of cells, then the storage capacity is improved, but the performance deteriorates
Solution Approach 1:
The pipeline configuration ensures continuous useful action by overlapping the erase operations of multiple blocks. While one block is being erased in the first stage, another block can simultaneously undergo verification or begin its erase operation in the second stage. This continuous processing eliminates idle time and maintains high productivity despite increasing storage capacity.
3Reliability
If the erase time period is extended, then the erase operation can be completed thoroughly, but the device may be erroneously judged as malfunctioned
Solution Approach 1:
The verification operation is performed as a preliminary action after each stage of the erase operation. By verifying the erase status after the first stage erase operation before proceeding to the second stage, the system can detect completion or errors early, ensuring reliable erase operation completion while minimizing the total time the device appears unresponsive.
4Quantity of substance
If the erase operation is performed on all cells of a block, then the free block is generated, but the power consumption increases
Solution Approach 1:
The erase operation is performed in stages, where the first stage erase operation erases a portion of the block and the second stage completes the erasure. This partial action approach allows the system to distribute power consumption over time and across multiple stages, reducing peak power requirements while still achieving complete erasure of all cells to generate free blocks.
Data Source
AI summary
A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.