Internal Data Load Voltage Adjustment for Flash Memory Read Accuracy
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Solution Overview
Problem
In non-volatile flash memory devices, there is a challenge in accurately reading data due to misprogramming and misreading issues caused by the programming of upper page data affecting the threshold voltage distributions of neighboring memory cells, leading to inaccurate data retention and increased error rates.
Innovation Solution
The solution involves adjusting the read pass voltages applied to neighbor word lines during an Internal Data Load (IDL) process, where one neighbor with an upper page programmed receives an increased voltage and the other neighbor with an upper page not yet programmed receives a decreased voltage, maintaining the neutral threshold voltage of the selected memory cells and improving read accuracy without impacting programming accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard read pass voltage is applied to neighbor word lines during IDL, then programming operation can proceed, but misreading errors increase due to threshold voltage shifts in selected memory cells
Solution Approach 1:
The patent applies parameter changes by adjusting the read pass voltage levels applied to neighbor word lines during IDL operations. Specifically, when a neighbor word line has its upper page programmed, a first read pass voltage (e.g., 0V) is applied, while when the upper page is not programmed, a second read pass voltage (e.g., 5V) is applied. This dynamic voltage adjustment compensates for threshold voltage shifts in selected memory cells caused by programming operations on neighbor word lines, thereby preventing misreading errors while maintaining accurate data retention.
2Measurement precision
If read pass voltage is increased to improve read accuracy, then misreading errors decrease, but programming accuracy of neighbor word lines deteriorates
Solution Approach 1:
The patent implements local quality by applying different read pass voltages to different neighbor word lines based on their programming state. The system locally adapts the voltage level for each neighbor word line: applying a first read pass voltage (e.g., 0V) to neighbor word lines with programmed upper pages and a second read pass voltage (e.g., 5V) to neighbor word lines without programmed upper pages. This localized voltage adjustment improves read accuracy for each specific neighbor while avoiding adverse effects on programming accuracy, as each neighbor receives the appropriate voltage treatment based on its state.
3Quantity of substance
If upper page programming is performed on neighbor word lines, then storage capacity is utilized, but threshold voltage distributions of selected memory cells shift causing misreads
Solution Approach 1:
The patent applies preliminary anti-action by preemptively adjusting the read pass voltage applied to neighbor word lines during IDL operations to counteract the threshold voltage shifts that will occur due to upper page programming. Before reading the selected memory cells after neighbor word line programming, the system applies appropriate read pass voltages (first voltage for programmed neighbors, second voltage for unprogrammed neighbors) to compensate for the expected threshold voltage distributions. This preliminary voltage adjustment prevents misreading errors caused by the programming-induced threshold shifts, thereby maintaining read accuracy while utilizing full storage capacity.
Data Source
AI summary
Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.