Memory Circuit Source Line Voltage Control for Write Disturbance
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Solution Overview
Problem
Memory circuits face challenges in avoiding large voltage stress across bitcells during programming modes, which can lead to write disturbance errors.
Innovation Solution
The solution involves separately controlling and supplying a voltage level higher than ground to the source lines of unselected bitcells, such as using a positive power voltage (VDD) or VDD/2, to alleviate voltage stress and prevent write disturbance errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source lines of unselected bitcells are connected to ground level voltage during programming mode, then the memory circuit can operate with simple voltage reference, but large voltage stress occurs across half-selected bitcells causing write disturbance errors
Solution Approach 1:
The source lines are segmented into multiple independently controllable groups, allowing different voltage levels to be applied to different segments. This enables selective voltage control where unselected source lines receive elevated voltages to prevent write disturbance, while selected source lines can maintain ground reference for normal operation.
Solution Approach 2:
The voltage parameter of source lines is dynamically changed based on selection state. During programming mode, the voltage level of unselected source lines is raised from ground (0V) to an elevated level (e.g., VDD/2 or VDD), which reduces the voltage stress across half-selected bitcells and prevents unintended programming.
2Reliability
If elevated voltage is supplied to source lines of unselected bitcells, then voltage stress across bitcells is reduced preventing write disturbance, but additional voltage control circuitry and power consumption increase
Solution Approach 1:
The voltage level adjustment is performed in advance before the programming operation begins. By pre-charging or pre-biasing the unselected source lines to elevated voltages before the programming pulse is applied, the system prevents write disturbance proactively rather than requiring complex real-time monitoring and adjustment during the programming process.
Solution Approach 2:
Instead of applying full programming voltage to all source lines, the invention applies a partial voltage elevation (e.g., VDD/2 or VDD rather than the full programming voltage) to unselected source lines. This partial action is sufficient to prevent write disturbance without the excessive power consumption that would result from applying full voltage levels universally.
3Ease of manufacture
If all source lines share a common ground reference, then the circuit design is simplified, but half-selected bitcells experience large voltage stress leading to write disturbance errors
Solution Approach 1:
An intermediate voltage level (such as VDD/2 or a dedicated intermediate reference) is introduced as a mediator between ground and the full programming voltage. This intermediary voltage is applied to unselected source lines, providing a middle ground that reduces voltage stress on bitcells without requiring complete redesign of the reference architecture.
Data Source
AI summary
A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.