Memory Sub-Block Segmentation for Yield and Disturb Control
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Solution Overview
Problem
In semiconductor memory devices, particularly in 3D memory structures, increasing block size to enhance storage capacity leads to reduced block yield, challenges in data allocation efficiency, and issues with garbage collection, as well as limited flexibility due to shared bit line and word line voltage signals, which can cause disturb effects on memory cells during operations like programming or erasing.
Innovation Solution
The memory device is organized into separate sub-blocks within each block, with independent sets of word line switching transistors and bit lines, allowing for independent control of word line voltage signals for each sub-block, enabling flexible operation and reducing the impact of defective components by isolating them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If block size is increased to enhance storage capacity, then storage capacity is improved, but block yield is reduced
Solution Approach 1:
The memory block is divided into multiple independent sub-blocks (first sub-block and second sub-block), each with separate word line switching transistors and bit lines. This segmentation allows the memory system to maintain high storage capacity while improving yield by isolating defects to specific sub-blocks rather than affecting the entire block.
2Quantity of substance
If block size is increased to enhance storage capacity, then storage capacity is improved, but data allocation efficiency deteriorates
Solution Approach 1:
By segmenting the block into sub-blocks with independent control, the system can allocate data more efficiently to specific sub-blocks based on access patterns and data requirements, improving overall data allocation efficiency while maintaining large storage capacity.
Solution Approach 2:
The independent word line switching transistors enable dynamic and flexible data allocation across different sub-blocks, allowing the system to adaptively manage data placement based on operational requirements rather than being constrained by fixed block-level allocation.
3Quantity of substance
If block size is increased to enhance storage capacity, then storage capacity is improved, but garbage collection performance deteriorates
Solution Approach 1:
The segmentation of the block into independent sub-blocks enables more granular garbage collection operations, where only the specific sub-blocks containing invalid data need to be processed rather than the entire block, significantly improving garbage collection performance while maintaining large storage capacity.
4Device complexity
If shared bit line and word line voltage signals are used, then device complexity is reduced, but disturb effects on memory cells increase
Solution Approach 1:
By providing separate word line switching transistors for each sub-block, the patent enables independent control of voltage signals to specific sub-blocks. This segmentation reduces disturb effects by allowing precise targeting of operations to only the necessary sub-blocks, while the shared bit lines maintain acceptable device complexity.
5Adaptability or versatility
If independent word line switching transistors are provided for each sub-block, then flexibility and reliability are improved, but device complexity increases
Solution Approach 1:
The patent divides the block into sub-blocks with independent word line switching transistors, achieving operational flexibility and reliability improvements. The segmentation allows independent control of each sub-block while maintaining a systematic and scalable architecture that manages device complexity through organized repetition of the sub-block structure.
Data Source
AI summary
A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.