NAND Flash Controller Error Bit Grouping for Data Integrity
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Solution Overview
Problem
Memory systems controlling nonvolatile memories, such as SSDs with NAND flash, face challenges in reducing the number of error bits as program/erase cycles increase, leading to degraded performance and data integrity.
Innovation Solution
A memory system that measures error bits for each word line, identifies and groups those exceeding a threshold, and adjusts program operation parameters based on average error bit counts to reduce errors, thereby suppressing the increase in error bits across the nonvolatile memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of program/erase cycles increases, then the memory system can store and retrieve more data, but the number of error bits increases leading to degraded data integrity
Solution Approach 1:
The patent changes program operation parameters (such as program voltage levels, pulse widths, or timing) based on the measured average number of error bits for each word line group. When error bits exceed a threshold, the controller adjusts the parameters to optimize programming conditions and reduce errors, thereby maintaining data integrity even as program/erase cycles increase
Solution Approach 2:
The patent implements a feedback mechanism where the controller measures error bits for each word line, identifies groups exceeding thresholds, calculates average error bit counts, and uses this information to dynamically adjust program operation parameters. This closed-loop control continuously optimizes programming to suppress error bit increase
2Device complexity
If uniform program parameters are used for all word lines, then the control logic is simple, but error bits increase across the entire memory as cycles progress
Solution Approach 1:
The patent applies different program operation parameters to different word line groups based on their specific error characteristics. Instead of uniform parameters, each word line group receives customized parameters tailored to its error profile, enabling localized optimization that suppresses error bit increase in problematic areas without affecting overall system complexity significantly
3Manufacturing precision
If program operation parameters are adjusted for each individual word line, then error reduction precision is maximized, but the device complexity and processing overhead increase significantly
Solution Approach 1:
The patent merges adjacent word lines into word line groups and applies uniform parameters to each group rather than individual word lines. This grouping strategy maintains sufficient error reduction precision while significantly reducing processing overhead and device complexity compared to individual word line adjustment, achieving an optimal balance between precision and complexity
Data Source
AI summary
According to one embodiment, each time the number of program/erase cycles of a block increases by a first number of times, a controller of a memory system measures the number of error bits of data read from a plurality of memory cells connected to each of a plurality of word lines. The controller identifies a word line group including a word line corresponding to the number of error bits which is greater than a threshold. The controller selects, based on an average number of error bits of the identified word line group, a parameter set to be applied to the identified word line group from a plurality of parameter sets. The controller changes, to the selected parameter set, a parameter set defining a program operation for the identified word line group.