Alternating Write Step Order for Memory Cell Disturb Reduction
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Solution Overview
Problem
In semiconductor memory devices, write disturb occurs when unselected memory cells are affected by the bias voltages used during write operations on selected cells, leading to interference and data integrity issues due to the high density of storage transistors in memory arrays.
Innovation Solution
A write disturb reduction method is implemented by alternating the order of the write logical '1' step and write logical '0' step in subsequent write operations on memory cells associated with the same group of bit lines, either by consistently alternating or randomly selecting the order for each operation, to minimize the impact on unselected memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density storage transistors are arranged in memory arrays, then storage capacity is improved, but write disturb to unselected memory cells increases
Solution Approach 1:
The patent applies periodic action by alternating the write step order (first logical state then second logical state vs. second logical state then first logical state) between adjacent memory pages. This periodic alternation ensures that unselected memory cells are not continuously exposed to the same logical state writes, thereby reducing write disturb while maintaining high-density storage capacity.
2Ease of operation
If the same write step order is used for all memory pages, then operation simplicity is improved, but write disturb to unselected cells increases
Solution Approach 1:
The patent implements dynamics by making the write step order adaptive rather than static. The control circuit automatically alternates the write step order based on the memory page being written, transforming from a fixed simple operation to a dynamic adaptive operation that reduces write disturb while remaining easy to implement through automated control.
3Productivity
If write operations are performed on all memory cells in a page, then write speed is improved, but interference to unselected cells increases
Solution Approach 1:
The patent applies local quality by differentiating the treatment of selected versus unselected memory cells through alternating write step orders. While all cells in a page receive write operations for high speed, the alternating pattern ensures that unselected cells experience varied logical states rather than persistent exposure to the same state, thereby reducing interference locally in unselected cells while maintaining overall write speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces write disturb by ensuring memory cells are not persistently exposed to the same logical state, thereby maintaining data integrity and preventing gradual or abrupt state changes in unselected cells.
Implementation Method 1
Data is stored in a charge storage film (e.g., a silicon oxide-silicon nitride-silicon oxide triple layer) in each storage transistor. Each storage transistor of a NOR memory string is read, programmed or erased by suitably biasing its associated word line and the common bit line it shares with other storage transistors in the NOR memory string.
Implementation Method 2
Data is stored in a charge storage film (e.g., a silicon oxide-silicon nitride-silicon oxide triple layer) in each storage transistor.
Data Source
AI summary
A semiconductor memory device implements a write disturb reduction method to reduce write disturb on unselected memory cells by alternating the order of the write logical “1” step and write logical “0” step in the write operations of selected memory cells associated with the same group of bit lines. In one embodiment, a method in an array of memory cells includes performing write operation on the memory cells in one of the memory pages to store write data into the memory cells where the write operation includes a first write step of writing a data of a first logical state and a second write step of writing data of a second logical state; and performing the write operation for each row of memory cells by alternately performing the first write step followed by the second write step and performing the second write step followed by the first write step.