NAND Flash Program Verify Drain Resistance Mimicry
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Solution Overview
Problem
In NAND MLC flash memory devices, the program verify operation causes cell degradation due to variations in drain resistance, leading to a potential 200 mV window loss, which is unpredictable and counterproductive to maintaining a tight voltage threshold window.
Innovation Solution
The solution involves modifying the Vpass voltage during the program verify operation by assuming half of the cells above the selected cell are programmed, thereby reducing the voltage applied to unselected word lines and mimicking the expected resistance, which can be adjusted based on the number of unselected cells above the selected cell, to maintain a consistent drain resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a high Vpass voltage is applied to turn on all cells in the NAND series string during program verify, then all cells can be accessed, but the higher Vpass voltage introduces more disturb conditions on the cells
Solution Approach 1:
The patent applies different voltage levels to different groups of cells based on their position in the string. Cells above the selected cell receive a first voltage level while cells below receive a second voltage level, creating local quality differences that reduce unnecessary disturb conditions while maintaining accessibility to the selected cell
Solution Approach 2:
The patent segments the NAND series string into two groups: cells above the selected cell and cells below the selected cell. This segmentation allows different voltage levels to be applied to each group, reducing the overall disturb conditions while maintaining cell accessibility
2Ease of operation
If the Vt of the highest cells is too high, then those cells cannot be turned on by Vpass, but increasing Vpass to turn them on introduces more disturb conditions
Solution Approach 1:
The patent recognizes that cells at different positions have different Vt requirements and applies different voltage levels locally. Cells above the selected cell (which may have higher Vt) receive a first voltage level while cells below receive a second voltage level, optimizing conductivity without excessive disturb conditions
3Productivity
If program verify is performed with unselected cells in erased state, then verify operation can be completed, but drain resistance variations cause cell degradation and voltage threshold window loss
Solution Approach 1:
The patent performs preliminary actions by setting specific voltage levels on unselected word lines before the program verify operation. This preliminary voltage configuration ensures that unselected cells are in an appropriate state during verify, preventing drain resistance variations and subsequent cell degradation
Solution Approach 2:
The patent applies preliminary anti-action by configuring unselected word lines with specific voltage levels that counteract the harmful effects of drain resistance variations. This prevents cell degradation and voltage threshold window loss before they can occur during the verify operation
Data Source
AI summary
A selected word line is biased with a program verify voltage. A predetermined quantity of unselected word lines that are between the selected word line and the bit line are biased with a modified Vpass voltage that is determined in response to a predetermined drain resistance. In one embodiment, the predetermined quantity is all of the word lines. Other embodiments can use smaller quantities. The remaining unselected word lines are biased with a normal Vpass voltage. The modified Vpass changes the resistance of the memory cells, acting as pass-gates during the program verification operation, to mimic a resistance of already programmed memory cells.