DRAM E-Fuse Memory Repair Circuit Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges with large area occupation and increased soft error rates due to the integration of fuse arrays and latches, which hinder high-speed operation and data storage efficiency.
Innovation Solution
The semiconductor memory device employs a DRAM-based architecture with E-fuses and DRAM memory cells, utilizing a repair operation unit and normal operation unit to manage and refresh data, allowing for efficient storage and access of repair information, thereby reducing the need for SRAM and minimizing chip area while maintaining high operating speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If SRAM latches are used to store fuse data, then data storage is achieved, but chip area increases significantly
Solution Approach 1:
The patent merges the fuse array and latch circuit into a single integrated structure where DRAM memory cells serve dual purposes: storing both fuse data and acting as latches. This integration eliminates the need for separate SRAM latch circuits, significantly reducing chip area while maintaining data storage functionality.
Solution Approach 2:
The DRAM memory cells are designed to perform multiple functions: they store fuse array data, act as latches for data retention, and participate in the boot-up operation. This multi-functionality replaces the need for dedicated SRAM latches, reducing overall chip area occupation.
2Quantity of substance
If fuse array size increases to store more data, then repair information capacity increases, but chip area increases
Solution Approach 1:
The patent combines the fuse array with DRAM memory cells in an integrated structure. The DRAM cells are positioned adjacent to the fuse array and share the same physical space, allowing the system to store more repair information without proportionally increasing chip area.
Solution Approach 2:
The patent utilizes vertical stacking and three-dimensional integration techniques where DRAM memory cells are arranged in multiple layers above and around the fuse array. This dimensional approach increases storage capacity without linearly increasing the chip footprint area.
3Ease of manufacture
If laser fuse circuits are used for programming, then fuse programming is achieved, but programming time increases
Solution Approach 1:
The patent replaces the mechanical laser-based fuse programming system with an electrical field-based E-fuse system. E-fuses are programmed by applying high electric fields to rupture gate dielectric layers, eliminating the need for laser equipment and significantly reducing programming time while maintaining manufacturing capability.
Solution Approach 2:
The patent changes the programming mechanism from optical (laser) to electrical (high electric field). This parameter change in the programming method enables faster programming speeds and eliminates the time-consuming laser processing step while achieving the same fuse programming function.
4Quantity of substance
If integration increases to store more fuse data, then repair information capacity increases, but soft error rate increases
Solution Approach 1:
The patent changes the storage medium from SRAM to DRAM, which has different electrical and physical characteristics. DRAM cells with larger capacitor structures exhibit lower sensitivity to neutron-induced soft errors compared to SRAM, thereby reducing the soft error rate while maintaining increased data capacity.
Solution Approach 2:
The patent employs a hybrid structure combining E-fuses with DRAM memory cells. This composite architecture leverages the radiation hardness of E-fuses for data storage and the larger capacitor structure of DRAM for reduced soft error sensitivity, achieving both high capacity and high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high-speed operation with reduced chip area usage and stable data storage by leveraging DRAM memory cells and E-fuses, addressing the limitations of conventional fuse arrays and latches.
Implementation Method 1
An E-fuse resembles a transistor, and ruptures its gate dielectric layer by applying a high electric field to a gate for it to be programmed.
Implementation Method 2
a plurality of first to third memory cells, each memory cell being a DRAM memory cell
Data Source
AI summary
A semiconductor memory device may include: a plurality of first to third memory cells, each memory cell being a DRAM memory cell; a plurality of fuses suitable for storing repair information for replacing failed first memory cells with corresponding second memory cells; a normal operation unit suitable for accessing and refreshing one or more of the first and second memory cells according to the repair information during a normal mode; and a repair operation unit suitable for providing the repair information from the fuses to the third memory cells during a boot-up mode, and for providing the repair information from the third memory cells to the normal operation unit and for refreshing the third memory cells during a normal mode.