Divisional Program Control Circuit for Phase Change Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional phase change memory apparatuses face challenges in efficiently programming multiple memory cells due to high peak current requirements, which can lead to program errors from ground bounce noise and increased transistor size, resulting in larger chip sizes and potential errors.
Innovation Solution
A semiconductor memory apparatus with a divisional program control circuit that divides the programming operation into multiple cycles, reducing peak current requirements and stabilizing the programming process by generating divisional programming enable signals and division codes to manage the programming of memory cells in a controlled manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If programming operation is performed on multiple memory cells simultaneously, then programming speed is improved, but peak current increases causing ground bounce noise and program errors
Solution Approach 1:
The programming operation is divided into multiple programming cycles, with each cycle programming a subset of memory cells. The divisional program control circuit generates divisional programming enable signals to control the timing and grouping of programming operations, thereby reducing peak current in each cycle while maintaining overall programming throughput.
2Productivity
If high peak current is applied for programming, then programming efficiency is improved, but transistor size increases leading to larger chip size
Solution Approach 1:
The programming operation is segmented into multiple cycles with reduced current requirements. By dividing the programming enable signal into divisional programming enable signals, the system achieves efficient programming without requiring high peak current, thus avoiding increased transistor sizes and larger chip area.
3Reliability
If programming enable signal is generated with preset cycle corresponding to program division times, then peak current is reduced and stability is improved, but control circuit complexity increases
Solution Approach 1:
The divisional program control circuit preliminarily divides the programming operation into multiple cycles before execution. By pre-generating divisional programming enable signals with appropriate timing cycles, the system ensures stable programming from the outset while managing control complexity through systematic signal generation rather than complex real-time control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The divisional program control circuit allows for stable and precise programming of memory cells by reducing peak current and preventing errors, thereby maintaining chip size and performance while ensuring reliable data recording.
Implementation Method 1
A phase change substance may be converted into an amorphous state or a crystalline state depending upon a temperature condition
Implementation Method 2
Joule's heat may be electrically generated by current flow through a conductor or a semiconductor to convert the GST between the amorphous state and the crystalline state
Data Source
AI summary
A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal; a divisional program control circuit configured to generate a divisional programming enable signal according to a predetermined number of program division times, in response to the program completion signal; and a controller configured to generate the programming enable signal in response to the divisional programming enable signal.