Memory Circuit Differential Read Margin and Cell Utilization
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Solution Overview
Problem
Existing memory circuits face challenges in improving data retention and cell utilization rate, as they rely on reference currents that do not adapt to changes in cell current distributions over time, leading to reduced read margins and inefficient cell usage.
Innovation Solution
A memory circuit design that incorporates a cell array with N rows of cells, where each row includes M+1 bit cells, with the (M+1)th bit cell storing opposite data of an ith bit cell. This design utilizes a sense amplifier array with differential input ports for reading stored data, comparing the current of adjacent cells in a differential structure to ensure a larger read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read circuit compares cell current with reference current to read data, then data reading function is achieved, but read margin decreases over time due to charge leakage and cell current distribution changes
Solution Approach 1:
The patent implements a feedback mechanism by using the (M+1)th bit cell to store the inverted data of the ith bit cell, creating a differential pair. The sense amplifier compares the currents of these two cells, where the reference current is dynamically replaced by the current from the opposite-stored cell. This feedback structure automatically compensates for drifts in reference current over time, maintaining stable read margins without requiring external calibration.
Solution Approach 2:
The patent changes the parameter of reference current from a fixed external reference to a dynamic internal reference derived from the cell array itself. By using the inverted data stored in the (M+1)th bit cell as the reference, the system adapts to changes in cell current distribution caused by charge leakage, temperature, and voltage variations, thereby maintaining consistent read margins throughout the product lifecycle.
2Reliability
If differential cells are used to improve read margin, then data retention improves, but cell utilization rate decreases due to adjacent cell storage requirements
Solution Approach 1:
The patent merges the reference current generation function into the cell array structure itself. Instead of using separate reference current circuits, the (M+1)th bit cell is integrated into the array to store inverted data and provide reference current. This merging eliminates the need for additional dedicated reference current circuitry, thereby improving cell utilization rate while maintaining the differential reading advantage.
Solution Approach 2:
The (M+1)th bit cell serves multiple functions: it stores inverted data for differential reading, provides reference current for comparison, and acts as part of the cell array structure. This multi-functionality reduces the overall resource consumption and improves cell utilization rate while maintaining high data retention performance.
Data Source
AI summary
This application discloses a memory circuit. Each row of cells includes M+1 bit cells. First to Mth bit cells normally store M-bit data; an (M+1) th bit cell stores opposite data of an ith bit cell; each row of sense amplifiers includes M sense amplifiers; one positive input end of an ith sense amplifier is connected with an output end of the ith bit cell; one negative input end of the ith sense amplifier is connected with an output end of the (M+1) th bit cell; two positive input ends of a jth sense amplifier are connected with an output end of a jth bit cell; two negative input ends of the jth sense amplifier are respectively connected with an output end of the (M+1) th bit cell and an output end of the ith bit cell. The memory circuit can improve data retention and increase the utilization rate of the cells.