Multi-Plane Memory Read Latency via Independent Plane Control
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Solution Overview
Problem
Existing memory devices face challenges in efficiently reading multiple planes concurrently due to restrictions on randomly selecting word lines and delays in outputting data, as well as limitations in customizing read voltages for each plane.
Innovation Solution
A common control circuit, such as a state machine, is configured to manage concurrent read operations across different planes, allowing for early output of single-bit memory cells in one plane and later output of multi-bit cells in another, with customized read voltages applied in each plane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrent read operations are performed across multiple planes, then productivity is improved, but device complexity increases due to coordination requirements
Solution Approach 1:
The memory device is divided into multiple independent planes, each capable of performing read operations simultaneously. Each plane has its own read circuitry that can operate independently, allowing concurrent reads without requiring complex centralized coordination. This segmentation enables parallel processing while keeping individual plane complexity manageable.
Solution Approach 2:
A common control circuit is designed to manage multiple planes using a unified control mechanism. The control circuit can selectively enable different planes and configure read parameters for each plane, providing multi-functional capability without requiring separate dedicated control circuits for each plane. This reduces overall device complexity while maintaining concurrent read capability.
2Loss of time
If read operations are performed on multiple planes simultaneously, then loss of time is reduced, but ease of operation deteriorates due to restrictions on randomly selecting word lines
Solution Approach 1:
Each plane is equipped with independent read circuitry that can be configured with customized read voltages and parameters specific to that plane's characteristics. This allows each plane to be optimized independently for its specific word lines and memory cells, maintaining operational flexibility while enabling concurrent reads. The local quality approach ensures that random word line selection remains easy within each plane without affecting other planes.
Solution Approach 2:
The system performs preliminary configuration of read parameters and voltage levels for each plane before initiating concurrent read operations. This preliminary setup ensures that each plane is properly prepared and configured for its specific read requirements, eliminating the need for complex real-time coordination during the actual read operation. Word line selection and voltage configuration are predetermined, simplifying the operation while enabling parallel execution.
3Measurement precision
If customized read voltages are applied to each plane, then measurement precision is improved, but device complexity increases due to additional voltage control circuitry
Solution Approach 1:
A common voltage control circuit is designed to provide customized read voltages to multiple planes simultaneously. The circuit can selectively apply different voltage levels to different planes based on their specific requirements, providing precise voltage control for each plane without requiring separate dedicated voltage control circuits. This multi-functional approach achieves measurement precision while minimizing the increase in device complexity through shared control infrastructure.
Data Source
AI summary
Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.