FDSOI Flash Memory Partitioning for Leakage Reduction

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Solution Overview

Problem

Current flash memory systems do not utilize fully depleted silicon-on-insulator transistor designs, which are known for minimizing leakage and optimizing performance, and there is a need for a partitioned flash memory chip that combines bulk and FDSOI regions to maximize area and minimize leakage.

Innovation Solution

The integration of fully depleted silicon-on-insulator (FDSOI) transistor designs into a flash memory system, partitioning the chip into bulk and FDSOI regions to enhance performance and reduce leakage, utilizing various types of FDSOI transistors such as standard fixed bias, flipped well fixed bias, and dynamic bias transistors, along with hybrid CMOS circuits to optimize voltage control and decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If fully depleted silicon-on-insulator transistor design is used, then leakage is minimized and performance is optimized, but device complexity increases due to partitioned chip structure

Engineering Contradiction:
Improveleakage minimizationVSAvoidpartitioned chip structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The chip is divided into distinct bulk region and FDSOI region, with each region optimized for specific functions. The FDSOI region contains circuits requiring low leakage (sensing amplifiers, column decoders), while the bulk region contains other memory cells and circuits, resolving the contradiction by spatially separating low-leakage requirements from standard operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different transistor types are deployed in different locations based on functional requirements. FDSOI transistors with fully depleted channels are used specifically where low leakage is critical, while bulk transistors are used elsewhere, providing locally optimized characteristics without requiring the entire chip to use the more complex FDSOI structure.

Inventive Principle:
Principle #3Local quality

2Reliability

If FDSOI transistors are integrated into flash memory system, then electrostatic control is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrostatic controlVSAvoidthin film fabrication
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The memory chip is segmented into FDSOI and bulk regions, allowing the thin-film FDSOI structure to be fabricated only where needed with high precision, while the bulk region uses more tolerant fabrication processes. This localized approach reduces overall manufacturing complexity while achieving the electrostatic control benefits of FDSOI in critical areas.

Inventive Principle:
Principle #1Segmentation

3Area of stationary object

If chip is partitioned into bulk and FDSOI regions, then chip area is maximized, but device complexity increases

Engineering Contradiction:
Improvechip areaVSAvoidregion partitioning
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The chip is segmented into bulk and FDSOI regions, allowing optimal placement of different circuit blocks in their most suitable region. This segmentation enables efficient space utilization by matching circuit requirements with region characteristics, maximizing the effective use of chip area while maintaining manageable complexity through clear regional functional assignment.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables improved performance and reduced leakage in flash memory systems by leveraging the electrostatic control and low leakage characteristics of FDSOI transistors, maximizing chip area and enhancing operational efficiency.

Implementation Method 1

leveraging the electrostatic control and low leakage characteristics of FDSOI transistors

Methodology Applied
Scientific EffectElectrostatic control: Electrostatics

Implementation Method 2

The cell 110 is erased, through a Fowler-Nordheim tunneling mechanism, by applying a high voltage on the erase gate 128

Methodology Applied
Scientific EffectFowler-Nordheim tunneling: Electron Beam

Implementation Method 3

A portion of electrons flowing across the gap between the word line 122 and the floating gate 124 acquire enough energy to inject into the floating gate 124

Methodology Applied
Scientific EffectHot electron injection: Electron Beam

Data Source

PatentEP3341937B1Fully depleted silicon on insulator flash memory design
Publication Date: 2024.10.30 SILICON STORAGE TECHNOLOGY INC
  • EP3341937B1 patent drawingFigure 1
  • EP3341937B1 patent drawingFigure 2
  • EP3341937B1 patent drawingFigure 3

AI summary

The present invention relates to a flash memory system wherein one or more circuit blocks utilize fully depleted silicon-on-insulator transistor designed to minimize leakage.