Partial Drain-Side Select Gate Voltage Control for NAND Memory Leakage
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Solution Overview
Problem
In NAND memory devices, shallow etching features can cause neighbor SGD interference, leading to unintended current leakage and compromising programming and sensing operations due to exposed select gates being influenced by neighboring electric fields.
Innovation Solution
The method involves electrically floating unselected partial SGD transistors and reducing the voltage of adjacent memory cells or transistors through a capacitance coupling effect, eliminating the need for negative voltage pumps by using a dummy word line, thereby preventing unintended activation of select gates during programming and sensing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shallow etching features are used to cut through portions of memory holes, then manufacturing complexity is reduced and device density is improved, but neighbor SGD interference occurs causing current leakage and compromising programming and sensing operations
Solution Approach 1:
The patent applies preliminary anti-action by electrically floating unselected partial SGD transistors before programming operations begin. This pre-floating prevents neighbor SGD interference from affecting selected memory cells during programming, thereby maintaining reliability while preserving the manufacturing simplicity of shallow etching features
Solution Approach 2:
The patent changes the electrical state parameter of unselected partial SGD transistors from grounded to electrically floating during programming operations. This parameter change eliminates the harmful electric field coupling between neighbor SGDs, preventing current leakage while maintaining the shallow etching structure's manufacturing advantages
2Reliability
If negative voltage pumps are used to prevent neighbor SGD interference, then programming and sensing reliability is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent extracts and eliminates the need for negative voltage pumps by using the inherent capacitance coupling between adjacent memory cells. The voltage reduction on adjacent cells naturally induces negative voltage on floating unselected partial SGDs through capacitive coupling, achieving interference prevention without adding complex voltage generation circuitry
Solution Approach 2:
The patent enables the memory device to self-regulate neighbor SGD interference through the natural capacitance coupling effect. By electrically floating unselected partial SGDs and reducing voltage on adjacent cells, the system uses its own existing electrical fields to prevent interference, eliminating the need for external negative voltage sources
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes neighbor SGD interference, reducing current leakage and improving the reliability of programming and sensing operations without the resource-intensive negative voltage source, allowing for more efficient use of memory device resources.
Implementation Method 1
reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect
Data Source
AI summary
A method of operating a memory device. The method includes the step of preparing a memory device that includes a first group of the memory holes with full SGD transistors and a second group of the memory holes with partial SGD transistors. The second group includes both a set of selected partial SGD transistors and a set of unselected partial SGD transistors. The method proceeds with electrically floating a first unselected partial SGD transistor of the set of unselected partial SGD transistors. With the at least one first unselected partial SGD transistor electrically floating, the method continues with reducing a voltage applied to at least one transistor or memory cell adjacent the first unselected partial SGD transistor such that a voltage of the first unselected partial SGD transistor is decreased through a capacitance coupling effect.