Dynamic Erase Voltage Adjustment for Nonvolatile Memory Wear Management

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Solution Overview

Problem

Semiconductor memory devices face challenges in optimizing erase operations to extend the lifespan of nonvolatile memory devices, as conventional methods do not effectively manage erase voltage levels based on cumulative effective wear levels and operation conditions, leading to inefficient wear leveling and potential device degradation.

Innovation Solution

A method and system that determine an erase mode based on the number of erase cycles and erase voltage used, and set an appropriate erase voltage level for each memory block, allowing for dynamic adjustment of erase voltage levels to manage wear leveling and extend device lifespan by selecting optimal write modes based on cumulative effective wear levels and operation parameters.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed erase voltage level is used for all erase operations, then the erase operation is simple to implement, but the wear leveling is inefficient and device lifespan is reduced

Engineering Contradiction:

Improvedevice lifespanVSAvoiderase operation complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic adjustment of erase voltage levels based on the cumulative effective wear level of memory blocks. The storage controller monitors wear levels and selectively applies different erase voltage levels (first, second, or third levels) depending on the specific wear condition of each memory block, transitioning from static to dynamic voltage control to optimize both device lifespan and operational complexity

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the erase voltage parameter based on wear level conditions. By adjusting the erase voltage level according to the cumulative effective wear level of memory blocks, the system optimizes the erase operation to extend device lifespan while managing the complexity through conditional parameter selection

Inventive Principle:

Principle #35Parameter changes

2Reliability

If high erase voltage is always applied to ensure complete erasure, then erase reliability is improved, but wear accumulation accelerates and device lifespan decreases

Engineering Contradiction:

Improveerase reliabilityVSAvoiddevice lifespan

Core Design Contradiction:

ReliabilityVSDuration of action of stationary object

Solution Approach 1:

The patent dynamically changes the erase voltage parameter based on wear level conditions. By adjusting the erase voltage level according to the cumulative effective wear level of memory blocks, the system optimizes the erase operation to extend device lifespan while managing the complexity through conditional parameter selection

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies partial erase voltage levels (first, second, or third levels) based on the specific wear condition of memory blocks. Instead of always applying maximum voltage, the system uses appropriate voltage levels matched to wear conditions, reducing unnecessary stress on already-worn blocks while maintaining sufficient erasure effectiveness

Inventive Principle:

Principle #16Partial or excessive action

3Duration of action of stationary object

If low erase voltage is used to reduce wear, then device lifespan is extended, but erase completeness may be compromised

Engineering Contradiction:

Improvedevice lifespanVSAvoiderase completeness

Core Design Contradiction:

Duration of action of stationary objectVSReliability

Solution Approach 1:

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent implements a feedback mechanism where the storage controller monitors the cumulative effective wear level of memory blocks and uses this information to select appropriate erase voltage levels. This feedback loop ensures that erase operations are adapted to current wear conditions, maintaining erase completeness while extending device lifespan

Inventive Principle:

Principle #23Feedback

4Productivity

If uniform wear leveling is applied to all memory blocks, then the management process is simplified, but optimal performance cannot be achieved for blocks with different wear states

Engineering Contradiction:

Improvewear leveling efficiencyVSAvoidwear management complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent applies different erase voltage levels to different memory blocks based on their individual cumulative effective wear levels. Instead of uniform treatment, the system tailors the erase operation to the specific wear condition of each block, optimizing wear leveling efficiency while managing complexity through localized adjustments

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9646705B2Memory systems including nonvolatile memory devices and dynamic access methods thereof

Publication Date: 2017.05.09 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of operating a memory device includes: determining an erase mode based on a number of erase cycles performed on a memory block and an erase voltage utilized to perform each erase cycle; and setting an erase voltage level for executing an erase operation on the memory block based on the determined erase mode.