Coupled-Gate Non-Volatile Memory Cell Design for Programming Speed
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Solution Overview
Problem
Conventional single gate non-volatile memory cells have inefficiencies in programming and erasing speed, small read current, and limited cycle durability, making it difficult to distinguish between program and erase states, thereby affecting reliability.
Innovation Solution
A non-volatile memory cell design using two transistors with coupled gates and shared drain region, where programming and erasing are achieved through controlled voltages applied to select lines and a bit line, and reading is done by measuring currents through select lines, enhancing programming speed, cycle durability, and read current margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional single gate non-volatile memory cell uses a single store transistor, then the device complexity is reduced, but the programming speed and erasing speed cannot be improved
Solution Approach 1:
The single store transistor is segmented into two separate transistors (first store transistor and second store transistor), each capable of independent operation for programming and erasing. This segmentation allows parallel operation during programming/erasing cycles, thereby improving speed while maintaining manageable device complexity through systematic design
2Reliability
If the conventional single gate non-volatile memory cell uses a single store transistor, then the device structure is simplified, but the number of programming and erasing cycles is limited
Solution Approach 1:
The single store transistor is divided into two separate transistors that can operate independently. During programming, one transistor is used while the other remains in a high-impedance state, and vice versa during erasing. This segmentation enables alternating use of the two transistors, effectively doubling the number of programming and erasing cycles before degradation occurs, thereby improving reliability
Solution Approach 2:
The two store transistors are used in an alternating periodic manner - one transistor is used for programming while the other is erased or remains idle, then they switch roles in subsequent cycles. This periodic action distributes the wear and degradation across both transistors over time, significantly extending the total number of programming and erasing cycles the memory cell can endure
3Reliability
If the conventional single gate non-volatile memory cell is used, then the device structure is simple, but the read current margin between program and erase states is narrow
Solution Approach 1:
The single store transistor is segmented into two transistors with separate control over their source regions. This allows independent optimization of the conduction paths for program and erase states, creating more distinct and separable current levels during read operations, thereby increasing the read current margin and improving reliability
4Productivity
If the conventional single gate non-volatile memory cell uses a single store transistor, then the device complexity is low, but the programming and erasing operation efficiency cannot be improved
Solution Approach 1:
The single store transistor is segmented into two transistors that can operate in parallel during programming and erasing operations. By controlling the source regions independently, the system can perform programming on one transistor while erasing or maintaining the other, effectively doubling the operation throughput and significantly improving overall operation efficiency
Solution Approach 2:
The two store transistors are utilized in a periodic alternating fashion during programming and erasing cycles. One transistor is actively programmed or erased while the other is prepared or maintained in a ready state, enabling continuous operation without idle time and maximizing the utilization of the memory cell resources, thereby improving operation efficiency
Data Source
AI summary
A non-volatile memory cell and methods for programming, erasing and reading thereof are provided. A non-volatile memory cell includes a well region having a first conductive type. A first transistor and a second transistor having a second conductive type are disposed on the well region, wherein a first gate of the first transistor is coupled to a second gate of the second transistor. The first transistor and the second transistor share a drain region, coupling to a bit line. A first source region of the first transistor and a second region of the second transistor are coupled to a first select line and a second line, respectively. A bit is stored in the first and second gates by controlling the first select line and the second line. A bit stored in the first and second gates is erased by controlling the first select line or the second line.