Semiconductor Memory Lateral Groove Charge Isolation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving operational reliability, particularly in the design and manufacturing of three-dimensional memory structures.
Innovation Solution
The semiconductor memory device incorporates a unique structure with a lower and upper interlayer insulating layer, channel patterns extending through these layers, and a conductive layer with specific areas facing the channel patterns. This configuration includes a data storage pattern in a lateral groove defined between the conductive layer and the channel pattern, where the interlayer insulating layers protrude more than the conductive layer, and the groove width decreases towards its end.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional memory structure is used to increase storage capacity, then the quantity of data storage patterns increases, but charge movement between adjacent data storage patterns occurs reducing reliability
Solution Approach 1:
The memory structure is divided into multiple independent memory cell strings with data storage patterns arranged in three-dimensional space. Each data storage pattern is separated by insulating structures (interlayer insulating layers and spacer patterns) that electrically isolate adjacent patterns, preventing charge leakage while maintaining high density storage capacity
Solution Approach 2:
Insulating structures serve as intermediary elements between adjacent data storage patterns. The interlayer insulating layers and spacer patterns act as electrical barriers that prevent direct charge movement between neighboring storage patterns, ensuring reliable operation while enabling close spacing for increased capacity
2Ease of manufacture
If the groove width is uniform to simplify manufacturing, then ease of manufacture improves, but charge movement between adjacent data storage patterns increases reducing reliability
Solution Approach 1:
The lateral groove width is designed with local variation: wider at the opening for easier manufacturing access and narrower toward the end for better charge isolation. This local quality change allows the groove to serve dual purposes - facilitating formation during manufacturing while ensuring electrical isolation between adjacent data storage patterns in the final structure
Solution Approach 2:
The groove width parameter is changed along the length of the groove, transitioning from a larger width at the opening to a smaller width toward the end. This parameter variation optimizes both manufacturing ease (wider opening) and charge isolation performance (narrower end section), resolving the contradiction between ease of manufacture and reliability
Data Source
AI summary
There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a lower interlayer insulating layer, an upper interlayer insulating layer, a channel pattern passing through the lower interlayer insulating layer and the upper interlayer insulating layer, a conductive layer facing the channel pattern between the lower interlayer insulating layer and the upper interlayer insulating layer, and a storage pattern arranged in a lateral groove, the lateral groove defined between the conductive layer and the channel pattern by the lower interlayer insulating layer and the upper interlayer insulating layer protruding toward the channel pattern more than the conducive layer, in which a distance from the conductive layer from the channel pattern decreases toward an end of the lateral groove.