Multi-Level Memory Cell Programming Verification

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Solution Overview

Problem

In four-level memory devices, the programming process can result in incorrect threshold voltage settings due to variations in source line voltage, leading to reduced read margins and incorrect verification of programmed states, especially for cells that reach the desired distribution first.

Innovation Solution

Implementing a method that uses test read voltages smaller than or equal to program voltages to verify the programmed state of cells, ensuring accurate verification by minimizing the impact of source line voltage fluctuations, and utilizing a page buffer architecture with additional latches for managing bit programming and verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If program voltages are applied to program memory cells in four-level devices, then two-bit data can be stored in each cell, but source line voltage variations cause incorrect threshold voltage settings and reduced read margins

Engineering Contradiction:
Improvestorage capacityVSAvoidprogramming accuracy
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The programming process is segmented into multiple phases: a first programming phase that programs cells to intermediate threshold voltages, followed by a second programming phase that programs cells to final threshold voltages. This segmentation allows verification at intermediate stages and prevents incorrect programming due to source line voltage variations, thereby maintaining high storage capacity while improving programming accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A preliminary programming phase is performed before the final programming phase. In this preliminary phase, cells are programmed to intermediate threshold voltages and verified. Only after successful verification do cells receive the final programming voltages. This preliminary action ensures that cells are correctly programmed before committing to final states, resolving the contradiction between storage capacity and programming accuracy.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If verification is performed during programming, then programming accuracy can be improved, but the programming process time increases

Engineering Contradiction:
Improveprogramming precisionVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Verification is performed periodically at specific phases of the programming process rather than continuously. The method includes a first programming phase with verification, followed by a second programming phase. This periodic verification approach maintains programming precision while minimizing the time penalty by verifying only at critical intermediate points rather than after every programming operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Verification is performed as a preliminary action before final programming voltages are applied. By verifying at intermediate threshold voltages first, the method ensures programming precision is achieved early, allowing the final programming phase to proceed efficiently without requiring additional verification time, thus balancing precision and time.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If read margins are increased to improve verification accuracy, then programming verification reliability improves, but the voltage ranges available for programming intervals are reduced

Engineering Contradiction:
Improveverification accuracyVSAvoidvoltage interval flexibility
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The voltage range is segmented into multiple programming phases with different voltage levels. The first programming phase uses voltages that provide sufficient read margins for accurate verification at intermediate threshold voltages. The second programming phase then applies different voltages to reach final threshold voltages. This segmentation allows each phase to be optimized independently, maintaining verification accuracy while preserving overall voltage interval flexibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The programming method dynamically adjusts voltage levels between phases. During the first programming phase, voltages are selected to maximize read margins for accurate verification. During the second programming phase, voltages are adjusted to reach final threshold values. This dynamic adaptation allows the system to maintain verification accuracy at each stage while preserving the ability to program across the full range of threshold voltages.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures accurate programming and verification of two-bit data in four-level memory cells by maintaining sufficient read margins and preventing threshold voltage shifts, thereby ensuring reliable data storage and retrieval.

Implementation Method 1

In non-volatile memory devices this is done by transferring a certain electrical charge in a floating gate of the cell

Methodology Applied
Scientific EffectCharge transfer: Conduction (electrical)

Implementation Method 2

A reading operation is carried out by comparing an electrical parameter, correlated with the current that flows through the cell

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS8971112B2Method of programming a multi-level memory device
Publication Date: 2015.03.03 MICRON TECHNOLOGY INC
  • US8971112B2 patent drawing
  • US8971112B2 patent drawing
  • US8971112B2 patent drawing

AI summary

Method of programming a multi-level memory cell may include transferring one or more values between an auxiliary latch of the multi-level memory cell and a most significant bit (MSB) latch of the multi-level memory cell and/or between the auxiliary latch and a least significant bit (LSB) latch of the multi-level memory cell while programming the multi-level memory cell.