Non-Volatile Memory Erasing via Well Voltage Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The erasing operation in non-volatile memory cells is disrupted due to capacitive coupling between the well and the word line, causing the word line voltage to rise prematurely, which prevents the negative voltage from reaching the required level for efficient erasing.
Innovation Solution
A semiconductor device with a negative voltage generating circuit for the word line and a positive voltage generating circuit for the well, where the positive voltage is applied after the negative voltage has reached a predetermined level, delaying capacitive coupling and ensuring efficient erasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a negative voltage is applied to the word line for erasing operation, then the charge can be erased from the floating gate, but the word line voltage rises prematurely due to capacitive coupling with the well
Solution Approach 1:
The patent applies a positive voltage to the well region before applying the negative voltage to the word line during the erasing operation. This preliminary action charges the well region in advance, which prevents the capacitive coupling from causing premature voltage rise on the word line when the negative voltage is subsequently applied. The pre-charged well acts as a voltage buffer that stabilizes the word line voltage throughout the erasing process.
2Device complexity
If the well is commonly provided in many memory cells, then the electrostatic capacitance of the well is extremely large, but this large capacitance causes the word line voltage to rise when the well is charged
Solution Approach 1:
The patent converts the harmful capacitive coupling effect into a beneficial mechanism by intentionally charging the well region with a positive voltage before the erasing operation. The large capacitance of the well, which normally causes harmful voltage rise, is instead used as a charge reservoir that stabilizes the word line voltage. The pre-charged well absorbs the capacitive coupling effect rather than allowing it to disrupt the erasing operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows the negative voltage to reach the necessary level for effective erasing, resulting in a more stable and faster memory cell array operation by preventing the word line voltage from rising to 0V prematurely.
Implementation Method 1
when an erasing operation is performed to the memory cell 12, that is, when the charge is erased from the floating gate 44, a negative electric potential is applied to the well 33 via the control gate 48 and the word line. Thereby, due to a Fowler-Nordheim tunneling phenomenon, electrons in the floating gate 44 tunnel to the p-type well 32 through the tunnel oxide film 42, thus erasing the charge in the floating gate 44.
Implementation Method 2
This may be due to capacitive coupling between the well 33 and the word line WL arranged on the well 33. Since the well 33 is commonly provided in many memory cells 12, an electrostatic capacitance (parasitic capacitance) of the well 33 is extremely large compared to that of the word line WL. Accordingly, the word line voltage Vword may be raised when the well 33 is charged.
Data Source
AI summary
Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.