NAND Flash Memory Discharge Circuitry for Power Loss Mitigation
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Solution Overview
Problem
Integrated circuit memory devices face challenges in managing power loss, particularly in NAND flash memory, where abrupt power drops can lead to information corruption and physical damage due to unstable voltage levels, with decreasing available time for discharge and increased resistive and capacitive effects as process scaling advances.
Innovation Solution
The implementation of enhanced discharge circuitry that allows for an extended effective range of supply voltage levels during power loss, enabling controlled discharge of access lines to mitigate voltage stress, including the use of energy stores and optimized control logic to manage discharge sequences across multiple thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process scaling is advanced to increase memory density, then memory capacity is improved, but resistive and capacitive effects increase reducing discharge time
Solution Approach 1:
The discharge circuit is segmented into multiple parallel discharge paths, each with its own discharge transistor. This segmentation allows simultaneous discharge of multiple access lines through different paths, effectively reducing the total discharge time despite increased RC effects from process scaling.
Solution Approach 2:
The patent introduces a time dimension to the discharge process by implementing staged discharge sequences. Different access lines are discharged at different times based on their voltage levels and discharge rates, creating a multi-phase discharge timeline that optimizes the overall discharge process while accounting for RC effects.
2Reliability
If discharge circuitry is enhanced to extend effective range of supply voltage levels, then reliability is improved, but device complexity increases
Solution Approach 1:
The discharge transistors are designed to serve multiple functions: they act as discharge paths during power loss events, function as access line drivers during normal operation, and can be selectively enabled based on voltage threshold detection. This multi-functionality reduces the need for separate dedicated discharge circuitry.
Solution Approach 2:
The discharge circuitry automatically activates when supply voltage drops below threshold levels, using the voltage detection mechanism already present in the memory device. The system self-regulates the discharge process without requiring external control signals, reducing the complexity of control logic.
3Reliability
If discharge of access lines is delayed to extend discharge time, then data corruption risk is reduced, but voltage stress on device increases
Solution Approach 1:
Different access lines are discharged with different priorities and timing based on their local conditions. The discharge circuitry selectively activates specific discharge paths for specific access lines depending on their voltage levels, discharge rates, and associated data importance, rather than applying a uniform discharge approach.
Solution Approach 2:
The system performs preliminary assessment of access line voltage levels and discharge characteristics before initiating discharge. High-voltage access lines are identified and discharged first through dedicated paths, while lower-priority lines are discharged subsequently, ensuring critical data is protected before voltage stress becomes dangerous.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution extends the time available for discharging access lines to safe voltage levels, reducing the risk of data corruption and physical damage during power loss events, even under increased resistive and capacitive effects from process scaling, thereby enhancing the reliability of memory devices.
Implementation Method 1
an energy store selectively connected to a supply voltage node and selectively connected to discharge circuitry
Data Source
AI summary
Memories including an array of memory cells, a local access line connected to a plurality of memory cells of the array of memory cells, a global access line, a transistor connected between the global access line and the local access line, and an energy store either selectively connected to a control gate of the transistor, or selectively connected to a control gate of a different transistor connected between the control gate of the transistor and a voltage node configured to receive a reference potential.