Multi-level Storage Algorithm for Flash Memory Disturb Control
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Solution Overview
Problem
Conventional multiple storage flash memory technology suffers from reduced program/erase accuracy and control over memory cell characteristics, leading to memory read errors due to indeterministic disturb of characteristics during programming or erasing, causing overlapping distributions of logic states in memory cells.
Innovation Solution
The system intelligently disturbs memory cells by determining desired characteristic states for each cell and successively or directly storing equivalent states in multi-cell memory devices, using gradation methods to mitigate read errors by controlling the overlap of distributions, with an analysis component determining the size of gradation and an artificial intelligence component facilitating the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If programming or erasing is performed on one bit of a memory cell, then the desired characteristic state is updated, but the characteristics of other bits are indeterministically disturbed
Solution Approach 1:
The system performs preliminary actions by updating characteristic states of multiple bits in a predetermined sequence before the disturb effect can propagate. By controlling the order of updates (e.g., updating bit 0 before bit 1, or updating from least significant bit to most significant bit), the system ensures that when one bit is programmed or erased, the other bits have already been set to their final states or are in a known state that can tolerate the disturb effect.
Solution Approach 2:
The system segments the program/erase operation into multiple sequential stages, where each bit is updated in a separate stage rather than simultaneously. This segmentation allows the system to control the disturb effect by isolating operations on individual bits, updating them one at a time in a controlled sequence, thereby preventing the harmful disturbance from affecting multiple bits at once.
2Productivity
If conventional programming methods are used, then storage speed is maintained, but control over distribution of memory cell characteristics is reduced
Solution Approach 1:
The system performs preliminary sorting and sequencing of the bits to be programmed or erased. Before the actual program/erase operation, the system determines the optimal update sequence based on the desired final state distribution. This preliminary action allows the system to maintain storage speed by preparing the update sequence in advance, while simultaneously achieving precise control over the characteristic distribution by following the predetermined sequence.
Solution Approach 2:
The system dynamically adjusts the program/erase operation sequence based on the current state of memory cells and the desired final distribution. Rather than using a fixed sequential approach, the system can adaptively determine which bits to update next, allowing it to optimize both speed and precision by dynamically responding to the actual state of the memory array during the operation.
3Quantity of substance
If multiple storage flash memory technology is used to increase density, then storage capacity is improved, but read errors increase due to overlapping distributions
Solution Approach 1:
The system performs preliminary updates of characteristic states in a predetermined sequence before performing the final read operation. By updating bits in a specific order (e.g., from least significant to most significant bit, or in groups that minimize distribution overlap), the system ensures that the final distribution of memory cell characteristics does not overlap, thereby preventing read errors while maintaining high storage capacity.
Solution Approach 2:
The system uses feedback mechanisms to monitor the distribution of memory cell characteristics during the program/erase operation. By continuously checking the state of memory cells and adjusting the update sequence accordingly, the system can prevent distribution overlap that would lead to read errors. The feedback loop ensures that high-density storage is maintained while read accuracy is preserved through real-time control of the characteristic distribution.
Data Source
AI summary
Providing systems and methods that reduce memory device read errors and improve memory device reliability by intelligently disturbing the memory cells during storage of their characteristic states. A specification component can determine a desired characteristic state for each cell of a plurality of multi-cell memory devices. A storage component can, alternatively, successively store an equivalent characteristic state in each cell of the plurality of multi-cell memory devices in stages, based on a cell's current characteristic state, or directly store the desired characteristic state of each cell of the plurality of multi-cell memory devices, based on an ordering of desired characteristic states of cells of the multi-cell memory devices. Further, a step component can gradate the equivalent characteristic state between successive storage stages. In this way, the overlap of distributions of electrical characteristics associated with different bits of one or more memory cells can be reduced.