Page Buffer Circuit Single Latch Multi-Phase Data Storage
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Solution Overview
Problem
Traditional page buffer circuits in memory arrays require multiple latches to store data across different phases of a multi-phase program operation, increasing the overall area of the integrated circuit and complicating data management.
Innovation Solution
A page buffer circuit design utilizing a single latch to store program data, program verify data, and preparation data across various phases of a multi-phase program operation, with control circuitry managing the latch to determine whether to program a memory cell in subsequent operations, and switch circuitry connecting sense and latch nodes to indicate programming success or failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple latches are used to store data across different phases of a multi-phase program operation, then data storage reliability is improved, but the area of the integrated circuit increases
Solution Approach 1:
The patent combines multiple latches into a single latch that stores different types of data (program data, program verify data, preparation data) at different phases of the multi-phase program operation. This merging reduces the total number of latches from multiple to one, thereby reducing the integrated circuit area while maintaining the ability to store all necessary data throughout the programming process.
Solution Approach 2:
The single latch is designed to perform multiple functions by storing different types of data at different phases. It serves as a program data storage element during the program phase, a program verify data storage element during the verify phase, and a preparation data storage element during the preparation phase. This multi-functionality allows one latch to replace what would traditionally require multiple specialized latches.
2Adaptability or versatility
If multiple latches are used to store different data types, then data management capability is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple data management functions into a single latch structure. Instead of having separate latches for program data, program verify data, and preparation data, the invention uses one latch that sequentially performs all these functions through controlled data loading and interpretation at different phases, thereby reducing device complexity.
Solution Approach 2:
The latch's function is made dynamic rather than static. The same physical latch structure changes its operational role dynamically based on the phase of the multi-phase program operation. Control circuitry dynamically configures the latch to store and interpret different types of data at appropriate times, enabling versatile data management without requiring multiple fixed-function latches.
Data Source
AI summary
A page buffer circuit is coupled to a bit line of a memory array. The page buffer circuit includes a latch storing different data during different phases of a multi-phase program operation. A preparation phase is after the program phase and after the program verify phase of the present multi-phase program operation. For the preparation phase, the control circuitry causes the latch to store the preparation data indicating whether to program the memory cell in a subsequent multi-phase program operation following the present multi-phase program operation. Results of the program verify phase, and contents of the latch at a start of the present multi-phase program operation, are sufficient to determine the preparation data.