3D Semiconductor Memory Devices with Protruding Insulating Patterns

The patent transitions from 2D planar memory cells to 3D vertically stacked memory cells, arranging multiple memory cell layers in the vertical direction. This dimensional change enables significantly higher integration density without requiring proportionally more expensive manufacturing equipment, as the stacking approach leverages existing lithography capabilities across multiple layers rather than requiring extremely high-priced immersion lithography or EUV for each additional bit.

The memory device is segmented into multiple discrete memory cell layers stacked vertically, with each layer containing memory cells formed by the same lithography process. This segmentation allows the manufacturing process to be repeated across layers using standard equipment, reducing the cost per bit compared to forming all memory cells in a single complex 2D layer that would require increasingly expensive lithography for higher density.

The patent forms a sacrificial pattern structure before forming the final memory cell structures. This preliminary sacrificial pattern enables subsequent self-aligned formation of tunnel insulating layers, charge storage layers, and blocking insulating layers, ensuring proper alignment and reducing defects. The sacrificial pattern is removed after serving its alignment function, leaving the desired memory cell structure with high reliability achieved through precise alignment without requiring complex alignment processes.

The patent uses a sacrificial insulating pattern as an intermediary structure during manufacturing. This intermediary pattern serves as a template for forming the data storage pattern and ensures proper spacing and alignment of vertical semiconductor patterns. By using this intermediary, the process achieves high reliability through consistent structure formation while maintaining relative manufacturing simplicity, as the sacrificial pattern can be formed and removed using standard processes.

Instead of increasing 2D pattern density to the point where immersion lithography or EUV equipment is required, the patent achieves higher integration density by stacking multiple memory cell layers in the vertical dimension. Each layer can be formed using conventional lithography equipment, avoiding the need for extremely high-priced apparatuses while still achieving significantly higher overall density through the third dimension.

The patent divides the high-density memory structure into multiple layers, each formed by conventional lithography processes. This segmentation allows the use of standard equipment for each layer formation step, avoiding the need for single-step ultra-fine patterning that would require immersion lithography or EUV equipment, thereby reducing manufacturing equipment costs while achieving high integration density through vertical stacking.