Solid-State Devices TRIZ Cases

An oxide semiconductor thin film transistor array substrate with a dual-layer structure enhances charge mobility and threshold voltage stability.

Tilt implantation creates a patterned mask on protrusions to define recesses, eliminating photolithography overlay errors and improving fabrication yield.

Narrow-band interference filters on sub-pixels transmit specific wavelengths to boost color saturation in display panels.

Non-conformal deposition and anisotropic etching form high aspect ratio openings without sacrificial fillings, reducing manufacturing complexity.

A thinned second semiconductor substrate attaches to a first insulating interlayer, enabling electrical connection via plugs through the layered structure.

Laser roughening of exposed TFT surfaces bypasses defective interconnects, eliminating costly laser CVD repairs and reducing luminance unevenness.

A repairing portion electrically connects the pixel electrode and scan line in an E-ink display using laser welding.

A light emitting display uses high thermal conductivity spacers to conduct heat from the pixel circuit to a shield cap.

Segmented light-blocking supporting members bridge substrates to stabilize thin fillers, resolving the trade-off between filling reliability and color gamut.

An electrostatic protective layer covers touch leads and encapsulation elements in a display panel to shield against static interference.

Segmented shading layers on opposing substrates prevent light leakage from misaligned conductive lines, improving panel yield without reducing brightness.

Applying pre-charge voltage to both selected and inhibited bit lines reduces peak current during programming, alleviating the need for oversized charge pumps.

Individual MEMS sensor packages mount orthogonally via mechanical interconnect features to form inertial measurement units.

Segmented active regions in an optoelectronic semiconductor chip reduce charge carrier density and material strain while maintaining efficiency.

A hybrid sol-gel gate insulating layer combines organic and inorganic materials to enhance dielectric constant in thin film transistors.

A support structure stabilizes electronic components during solder reflow, preventing tilt angles that compromise electrical connection reliability.

A separation type unit pixel design minimizes the charge transfer path between photodiode and floating diffusion area.

Shielding member blocks impurities entering the panel part from the hinge area during folding operations.

A semiconductor device forms a substrate recess for a non-volatile gate stack, resolving HKMG compatibility issues with taller logic structures.

A vanadium dioxide threshold switch delivers current-controlled negative differential resistance without electroforming.

Segmented charge storage regions in the memory structure reduce second bit effect and program disturbance.

Specific emission layer compounds facilitate balanced charge injection in organic light emitting diode displays.

Optimized dummy gate parts form on peripheral regions to match cell region profiles.

A method fabricates semiconductor microstructures using sequential anisotropic and isotropic etching steps on Group III nitride layers.

Point cusp magnetron physical vapor deposition forms magnetic tunnel junctions on three-dimensional pillars for nonvolatile memory devices.

A three-mask manufacturing method for IPS thin-film transistor array substrates reduces fabrication steps by merging electrode formation operations.

A sequentially abutting OLED array substrate structure with a refractive index matched filling layer enhances light exit efficiency.

Replacing Zener diodes with an N-P-N structure reduces clamping voltage while maintaining low capacitance for integrated circuit protection.

A nonvolatile memory device creates air gaps between gate structures to lower coupling capacitance.

Auxiliary structures guide continuous organic semiconductor growth to eliminate lithography damage and enhance charge mobility.

Air voids in a porous scattering layer redirect substrate-trapped light to boost outcoupling efficiency from 20% to 65%.

Segmented glass barriers block moisture ingress in flexible displays while preserving substrate bendability.

Strategic blocking elements between adjacent sub-pixels prevent color mixing from evaporation shadows, ensuring uniform organic layer distribution.

Phase change device isolates contacts by modifying material state, reducing fabrication complexity and configuration time.

A fin selector with gated RRAM structure improves resistance distribution and memory window margins.

Convex and concave overcoating portions alter light paths in top emission OLEDs, reducing power consumption from trapped internal light.

Asymmetric hard masks reduce central region aspect ratios in split gate flash memory cells to improve inter-layer dielectric filling.

Stacked organic photoactive layers absorb specific wavelengths to maintain sensitivity despite reduced pixel absorption area.

Nesting a liquid crystal lens within the encapsulation layer reduces device thickness while polarizing film absorbs ambient light to minimize reflection.

Self-aligned spacers mask substrate etching to position recessed gates, reducing surface area and eliminating photolithography overlay constraints.

Merging source, drain, and pixel electrodes into one unitary IGZO structure eliminates multiple mask steps to simplify fabrication.

A first electrode acts as a fuse to ablate and isolate shorted pixels in an OLED lighting device.

Bridge structures between support pillars prevent electrical shorting from incomplete insulator filling in high-density vertical memory arrays.

A transparent partition wall layer sits above a light shielding layer to separate color filter materials during inkjet printing.

Island-shaped spacers support mask layers during deposition to maintain structural integrity.

A hybrid memory array combines mask programmable and electrically programmable anti-fuse cells to enable fast manufacturing programming.

Multi-layer isolation structures resist hydrofluoric acid erosion, maintaining uniformity and electrical performance in dense FinFET devices.

Thermal and ISSG oxidation form sacrificial oxide films to prevent foreign substance adhesion that causes incomplete etching in semiconductor manufacturing.

A semiconductor memory device uses segmented global and local bit lines to control voltage across three-dimensional transistor arrays.

Varying stack thickness between electrodes optimizes the micro-cavity, boosting emission efficiency while reducing color shift across viewing angles.

A flip-around switch circuit reduces charge-injection errors in sensor front-ends.

A polycycloolefinic polymer dielectric enables photo-patterning via controlled isomerization.

A boost capacitor stabilizes the driving voltage in an OLED pixel circuit to maintain consistent current output.

Protruding insulating patterns in a 3D semiconductor memory structure reduce manufacturing complexity and defects while increasing integration density.

A host layer performs charge transport and light emission within an organic light emitting diode structure.

A recess and protrusion-shaped microstructure diffracts incident light to enhance charge separation at the organic semiconductor interface.

Rapid gas cycling in a turntable apparatus deposits dense titanium nitride films while maintaining high productivity.

InGaZnO amorphous oxide semiconductor enables high electron mobility on flexible resin substrates.

Pyrrolidine-based compounds in a mixed layer balance carrier injection to enhance exciton trapping and extend device lifespan.

A light emitting device package integrates a bonding member fixing layer with through regions to secure the light emitting device on the heat radiating member.

A segmented data line configuration with peripheral insulation protects conductive traces from physical damage during testing operations.

Stepped pad structure aligns thick portions diagonally while bonding thin portions in stacked semiconductor devices.

A display substrate design uses varying insulating layer thicknesses to ensure proper etchant permeation across electrode blocks.

Vertical decoder merges multiple string drivers into a shared unit, reducing power consumption and device complexity in 3D NAND memory arrays.

A rigid backing substrate supports a handle during cleaving, reducing surface roughness on transferred films.

Protruding silicide layers between impurity regions and plugs lower contact resistance while maintaining high integration density.

An LED electrode coating absorbs harmful 400-410 nm radiation, protecting the emission layer from environmental damage and extending device lifespan.

A boron film mask enables selective etching of semiconductor layers using chlorine gas patterns.

Varying interdigitated capacitor digit widths concentrates conductive material near bars to minimize current loss while maximizing capacitance density.

Segmented natural and rapid oxidation of aluminum creates uniform resistance in scaled MTJ arrays.

A recessed light blocking portion on the planarization layer shields the active layer from incident illumination.

Segmented doping in a super steep retrograde well suppresses punchthrough while maintaining uniform threshold voltage along the fin height.

A silver cathode OLED uses a polar matrix mixed layer with electropositive metal dopants to enhance electron injection efficiency.

A panel structure uses conductive plugs to connect power lines and source electrodes within a transistor array.

Side surface electrode connections eliminate complex via-holes in non-conductive substrates, reducing manufacturing costs for light-emitting devices.

A composite metal oxide anti-reflection laminate reduces current leakage and structural damage in backside illuminated image sensors.

Dual-width banks control liquid organic deposition to create a flat emitting surface.

Asymmetric trench formation via an auxiliary polymer layer resolves gap-fill complexity and reduces interference between memory cells.

Distinct threshold voltages on shared drain select transistors simplify the alternating stack structure and reduce manufacturing complexity.

Surface functionalization of transparent conducting oxides reduces the hole injection barrier, eliminating extra organic layers and lowering operating voltage.

Lower valence dopant adjusts oxygen affinity to balance set and reset voltages.

A semiconductor patterning method forms islanding and line features simultaneously using a shared mask structure.

Femtosecond laser inspection detects sealing defects by measuring reflected light intensity and voltage parameters.

Varying the second insulative layer thickness above bottom wiring in white sub pixels prevents short circuits and overcurrents caused by impurities.

Grooves in the OLED array substrate disconnect the CVD film layer at shadow regions, preventing thin film extension that compromises device cutting reliability.

Silicon oxynitride charge-blocking regions and voids between vertically-stacked memory cells reduce charge leakage and capacitive coupling.

Aluminum-based amorphous metal particles replace silver in conductive inks, reducing manufacturing costs while maintaining oxidation resistance.

Coupling resistive memory elements to vertical fin transistors reduces area penalties and circuit complexity in neuromorphic crossbar arrays.

Differentiated barrier rib portions prevent ink mislanding and encapsulation layer defects by controlling liquid flow during manufacturing.

A semiconductor device distributes pass transistors across stacked substrate layers to reduce component count and improve high-speed operation.

A semiconductor element integrates a temperature detecting element on the substrate to monitor heat generation from current flow.

Segmenting the passivation layer into distinct regions prevents color uniformity reduction and viewing angle deterioration while maintaining device reliability.

A step compensation layer bridges thickness differences between light-blocking and pixel regions, reducing external reflectivity while preserving flatness.

Segmented partition walls with tailored surface energy confine and distribute ink, reducing high-resolution printing complexity.

A thin film transistor array panel uses a horizontal connection member to link the common voltage line and common electrode.

Curved flexible OLED structure disrupts total internal reflection to improve light extraction efficiency.

A third semiconductor layer with a Ga-face surface shields the active layer during device fabrication.

Inner and external heat dissipation layers connected through substrate holes reduce heat retention in light emitting elements, extending operational lifespan.

A memory refresh circuit compensates potential changes using oxide semiconductor transistors to retain multilevel data states.