IPS TFT Array Substrate Three-Mask Manufacturing Process
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Solution Overview
Problem
The high fabrication cost and extended time required for manufacturing in-plane switching (IPS) thin-film transistor (TFT) array substrates due to the need for multiple mask-involved operations in the existing processes.
Innovation Solution
A method for manufacturing an IPS TFT array substrate that reduces the number of mask-involved operations by using a three-step process: forming gate, scan, and pixel electrodes with a first mask, patterning a gate insulation and semiconductor layer with a second mask, and forming source-drain electrodes with a third mask, utilizing materials like molybdenum and copper for improved electrical conductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple mask-involved operations are used in the fabrication process, then the manufacturing precision and electrode pattern accuracy are improved, but the fabrication cost and manufacturing time increase
Solution Approach 1:
The patent combines multiple electrode formation operations into a single mask step. Specifically, the first mask is used to simultaneously form the gate electrode, scan electrode, and pixel electrode patterns, eliminating the need for separate mask operations for each electrode type. This merging approach maintains pattern accuracy while reducing the total number of mask steps from four or more to just one.
Solution Approach 2:
The single first mask serves multiple functions by defining patterns for different electrode types (gate, scan, and pixel electrodes) in one operation. This multi-functional mask approach replaces what would traditionally require multiple specialized masks, each dedicated to forming a specific electrode pattern, thereby reducing process complexity while maintaining precision.
2Manufacturing precision
If multiple mask-involved operations are used in the fabrication process, then the electrode pattern accuracy is improved, but the fabrication time is extended
Solution Approach 1:
The patent merges multiple sequential mask operations into a single parallel operation. By forming all electrode patterns (gate, scan, and pixel electrodes) simultaneously using one mask, the fabrication process eliminates the sequential time required for multiple separate mask steps, thereby accelerating production while preserving pattern accuracy through proper mask design.
Solution Approach 2:
The single mask is designed in advance to contain all necessary pattern definitions for different electrode types. This preliminary design approach allows all electrode patterns to be formed in one operation rather than requiring multiple sequential mask steps, thus reducing fabrication time while maintaining the precision needed for proper electrode alignment and function.
3Manufacturing precision
If multiple mask-involved operations are used in the fabrication process, then the pattern definition accuracy is improved, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple mask fabrication and application operations into a single integrated process step. By using one mask to define all electrode patterns simultaneously, the manufacturing process reduces the total number of masks required, lowering material costs and reducing the cumulative cost of multiple mask alignment and application operations while maintaining pattern definition accuracy.
Solution Approach 2:
The single mask is designed to perform multiple pattern definition functions simultaneously, creating gate, scan, and pixel electrode patterns in one operation. This multi-functional approach reduces the total number of masks needed compared to traditional methods requiring separate masks for each electrode type, thereby reducing overall manufacturing cost while preserving the precision needed for proper electrode formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the manufacturing time and cost while maintaining excellent electrical properties, achieving a simpler and more cost-effective process with only three mask operations compared to the traditional methods.
Implementation Method 1
depositing a first metal layer on the backing plate with physical vapor deposition
Implementation Method 2
coating a second metal layer on the predetermined gate electrode pattern and the predetermined scan line pattern to form the gate electrode and the scan line, wherein the second metal layer has electrical conductance greater than electrical conductance of the first metal layer
Data Source
AI summary
The present invention provides an IPS TFT array substrate and a manufacturing method thereof. The manufacturing method of an IPS TFT array substrate of the present invention includes: forming a gate electrode, a scan line, a pixel electrode, and a common electrode with a first mask-involved operation, forming a first through hole and a second through hole in the gate insulation layer and an active layer with a second mask-involved operation, and forming a source electrode, a drain electrode, a data line, and a common electrode line with a third mask-involved operation. The present invention uses only three mask-involved operations to complete the manufacturing of an IPS TFT array substrate. Compared to the state of the art, the number of masks used is reduced, the manufacturing time is shortened, and thus the manufacturing cost is lowered. The IPS TFT array substrate of the present invention has a simple manufacturing process, a low manufacturing cost, and excellent electrical properties.