3D NAND Memory Common Bit Line Drain Select Transistors
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Solution Overview
Problem
Current three-dimensional non-volatile memory devices, such as vertical NAND strings, face challenges in efficiently configuring and connecting drain select transistors with varying threshold voltages within the same memory block, which affects the device's operational efficiency and complexity in manufacturing.
Innovation Solution
The configuration of alternating stacks of insulating and conductive layers over a substrate, where specific drain select transistors are formed with distinct threshold voltages, and a common bit line is connected to multiple drain regions, allowing for a series connection of memory cell charge storage transistors with different threshold voltage transistors, simplifying the memory device structure and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple drain select transistors with varying threshold voltages are configured within the same memory block, then the operational efficiency and control precision are improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines multiple drain select transistors (first drain select transistor and second drain select transistor) into a single memory block, where they share common bit lines and are integrated within the same alternating stack structure. This merging approach enables coordinated operation of transistors with different threshold voltages to improve reliability while maintaining a unified device architecture that manages complexity through systematic integration rather than separate discrete components
Solution Approach 2:
The drain select transistors with varying threshold voltages serve multiple functions within the memory block: they enable selective access to different NAND strings, provide threshold voltage differentiation for various operational modes (read, program, erase), and share common bit line infrastructure. This multi-functionality improves operational efficiency by allowing a single configuration to handle diverse memory operations without requiring separate dedicated structures for each function
2Manufacturing precision
If multiple drain select transistors with varying threshold voltages are configured within the same memory block, then the control precision over threshold voltages is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent implements local quality by assigning different threshold voltages to specific drain select transistors within the memory block based on their functional requirements. The first drain select transistor and second drain select transistor have different threshold voltages tailored to their respective roles in accessing different NAND strings or handling different operational modes. This localized differentiation of electrical properties enables precise control over threshold voltages where needed while maintaining standard manufacturing processes for the overall device structure
Solution Approach 2:
The invention utilizes parameter changes by varying the threshold voltage parameter of drain select transistors within the same memory block. Through controlled adjustments in transistor design parameters (such as channel doping, gate oxide thickness, or transistor dimensions), the patent achieves different threshold voltage characteristics for different drain select transistors, enabling precise control over device behavior while using established semiconductor manufacturing techniques
3Ease of manufacture
If a common bit line is connected to multiple drain regions, then the device structure is simplified and ease of manufacture is improved, but the operational complexity may increase
Solution Approach 1:
The patent merges multiple drain regions (first drain region and second drain region) to share a common bit line connection. This consolidation reduces the number of separate bit line structures needed, simplifying the overall device architecture and reducing manufacturing steps. The common bit line serves multiple drain regions simultaneously, decreasing interconnect complexity while maintaining the ability to selectively access different NAND strings through the threshold voltage differentiation of associated drain select transistors
Data Source
AI summary
A memory device includes an alternating stack of insulating layers and electrically conductive layers. Vertical NAND strings are formed through the alternating stack, each of which includes a drain region, memory cell charge storage transistors, and a pair of drain select transistors in a series connection. A common bit line is electrically connected to drain regions of two vertical NAND strings. The drain select transistors of the two vertical NAND strings are configured such that drain select transistors sharing a first common drain select gate electrode provide a higher threshold voltage for one of the two vertical NAND strings, and drain select transistors sharing a second common drain select gate electrode provide a higher threshold voltage for the other of the two vertical NAND strings. The different threshold voltages can be provided by a combination of a masked ion implantation and selective charge injection.