Low Capacitance TVS Using N-P-N Avalanche Structure
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Solution Overview
Problem
Conventional transient voltage suppressors (TVS) face challenges in achieving low clamping voltage and breakdown voltage while maintaining low capacitance and small device package size, which is essential for protecting integrated circuits from overvoltage conditions such as electrostatic discharge and lightning strikes.
Innovation Solution
The implementation of an N-P-N structure instead of a Zener diode as an avalanche diode, using an n+ substrate to facilitate integration and reduce breakdown voltage, allowing for adjustable gain and thickness of the p+ implant layer to achieve desired breakdown and clamping voltage characteristics without increasing reverse leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Zener diode is used to achieve low breakdown voltage, then clamping voltage is reduced, but device capacitance increases
Solution Approach 1:
The patent changes the fundamental operating principle from Zener breakdown to avalanche breakdown mechanism. By using an N-P-N bipolar transistor structure with carefully controlled base width and doping profiles, the device achieves low breakdown voltage through avalanche multiplication rather than Zener effect, thereby reducing capacitance while maintaining low clamping voltage
Solution Approach 2:
The patent replaces the Zener diode structure with an N-P-N bipolar transistor structure. This substitution enables the use of avalanche breakdown mechanism instead of Zener breakdown, fundamentally changing the physical mechanism to achieve the desired low breakdown voltage with lower capacitance
2Quantity of substance
If Zener diode size is reduced to lower capacitance, then device package size decreases, but breakdown voltage control becomes difficult
Solution Approach 1:
The patent implements local quality variations through differentiated doping profiles in the base and collector regions, and through controlled base width variations. These local structural differences enable precise control of avalanche multiplication characteristics and breakdown voltage without increasing overall device size
Solution Approach 2:
The patent employs multiple parameter optimizations including base width, doping concentrations, and junction depths to precisely control breakdown voltage. By adjusting these parameters in the N-P-N structure, the device achieves reliable breakdown voltage control at small sizes
3Reliability
If avalanche diode breakdown voltage is reduced to improve clamping voltage, then protection performance improves, but reverse leakage current increases
Solution Approach 1:
The patent optimizes the base width and doping profile parameters to achieve a balance between breakdown voltage and reverse leakage current. By carefully controlling the base region characteristics and using avalanche breakdown mechanism, the device achieves low clamping voltage while maintaining acceptable reverse leakage performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the breakdown voltage below 6V, thereby lowering the clamping voltage, while maintaining low capacitance and small device packaging, supporting a wider range of applications with improved protection for integrated circuits.
Implementation Method 1
The Zener diode 101 has a large size and functions as an avalanche diode from the high voltage terminal, i.e., terminal Vcc to the ground voltage terminal, i.e., terminal Gnd. The term Zener and Avalanche will be used interchangeably hereinafter to describe a diode that exhibits avalanche breakdown properties.
Data Source
AI summary
A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.