Semiconductor Device NVM Logic Integration Recess
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Solution Overview
Problem
The integration of high dielectric constant metal gate (HKMG) scheme with non-volatile memory (NVM) cells is incompatible due to the taller gate stack of NVM cells, which is not compatible with the conventional CMP processes used in logic gate stacks, leading to incompatibility in fabrication processes.
Innovation Solution
A semiconductor device and method where a recess is formed in the substrate for the NVM cell, allowing the non-volatile gate stack to be lower than the logic gate stack, enabling separate and compatible fabrication processes for both without impacting the control gate or logic transistor, using a NVM-first process that forms the non-volatile gate stack before the logic gate stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the conventional CMP process is used for logic gate stacks, then the logic transistor fabrication is achieved, but the taller NVM gate stack cannot be integrated due to coplanarity requirements
Solution Approach 1:
The substrate is divided into a memory region and a logic region, allowing different gate stack structures to be formed in separate areas. The NVM cell with taller gate stack is formed in the memory region while the logic transistor with standard gate stack is formed in the logic region, eliminating the coplanarity conflict that would exist if a single uniform structure was used across the entire substrate.
Solution Approach 2:
Different gate stack configurations are implemented in different regions of the substrate. The memory region contains the NVM cell with its specific taller gate stack structure, while the logic region contains the HKMG logic transistor with its standard gate stack structure. This allows each region to have the optimal local structure for its specific function without compromising the other.
2Reliability
If the NVM cell gate stack is made taller for NVM functionality, then NVM performance is improved, but compatibility with HKMG logic fabrication process is lost
Solution Approach 1:
The device is segmented into distinct memory and logic regions with different gate stack heights. The NVM cell in the memory region maintains its taller gate stack structure necessary for NVM operation, while the logic transistor in the logic region uses the standard HKMG gate stack structure, allowing both to be fabricated using compatible processes for their respective regions.
Solution Approach 2:
The solution moves from a two-dimensional coplanar constraint to a three-dimensional stepped structure. By allowing the gate stacks to exist at different heights (creating a step difference between memory and logic regions), the taller NVM gate stack can coexist with the standard logic gate stack without requiring coplanarity, thus maintaining both NVM functionality and fabrication compatibility.
3Reliability
If separate fabrication processes are used for NVM and logic transistors, then each component can be optimized, but process complexity increases
Solution Approach 1:
The fabrication processes for NVM and logic transistors are merged into a single integrated process flow. By forming the NVM cell gate stack first in the memory region and then forming the logic transistor gate stack in the logic region using the same HKMG process, the need for separate fabrication sequences is eliminated, reducing overall process complexity while maintaining optimization for both component types.
Solution Approach 2:
The NVM cell gate stack is formed preliminarily before the logic transistor gate stack. This preliminary formation of the NVM structure first allows subsequent logic transistor fabrication to proceed without interference, as the taller NVM gate stack is already in place and can serve as a reference or barrier during the logic region processing.
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.