Vertical FinFET Resistive Memory Integration for Neuromorphic Computing
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Solution Overview
Problem
Current resistive memory technologies face challenges in integrating multiple resistive memory elements with vertical transport fin field effect transistors (VT FinFETs) efficiently, particularly in neuromorphic computing and high-density non-volatile memory applications, where area penalties and complex periphery circuits are required for differential weights.
Innovation Solution
The integration of two resistive memory elements (ReRAM cells) electrically coupled to a top source/drain of a vertical transport fin field effect transistor (VT FinFET), utilizing a hardmask fin template for self-alignment and lateral epitaxial growth of source/drain structures, allowing for differential weights without area penalties and enabling a crossbar array configuration for neuromorphic computing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple resistive memory elements are integrated with VT FinFETs using conventional methods, then memory density can be increased, but area penalties and circuit complexity increase
Solution Approach 1:
The patent merges multiple resistive memory elements (ReRAM cells) with a single VT FinFET into an integrated structure where two ReRAM cells are electrically coupled to the top source/drain of one VT FinFET. This consolidation reduces the number of separate transistor-memory element combinations needed, thereby decreasing circuit complexity while maintaining or increasing memory density.
Solution Approach 2:
The VT FinFET structure serves multiple functions simultaneously: it acts as a select transistor for row decoding and also provides differential weight control for two ReRAM cells. This multi-functionality eliminates the need for separate periphery circuits that would otherwise be required to control differential weights, reducing overall circuit complexity.
2Quantity of substance
If multiple resistive memory elements are integrated with VT FinFETs using conventional methods, then memory density can be increased, but area requirements increase
Solution Approach 1:
The patent transitions from planar integration to vertical integration by extending the FinFET structure vertically and coupling ReRAM cells to the top source/drain region. This vertical stacking approach allows multiple memory elements to share the same footprint area, increasing memory density without proportionally increasing the chip area.
Solution Approach 2:
The ReRAM cells are nested within the three-dimensional structure of the VT FinFET, with memory elements positioned in the vertical dimension above the substrate. This nesting arrangement allows multiple ReRAM cells to be integrated within the volume defined by a single FinFET structure, reducing the area required per memory element.
3Manufacturing precision
If lateral epitaxial growth is used for source/drain structures, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
A hardmask fin template is formed on the vertical fin before the epitaxial growth process. This template serves as a pre-established alignment reference that guides the subsequent lateral epitaxial growth of source/drain structures, ensuring precise positioning without requiring complex real-time alignment procedures during manufacturing.
Solution Approach 2:
The lateral epitaxial growth process is self-aligned to the hardmask fin template, meaning the source/drain structures automatically position themselves relative to the template during growth. This self-alignment mechanism eliminates the need for additional alignment steps and reduces process complexity while maintaining high manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient integration of multiple ReRAM cells with VT FinFETs, reducing area requirements and simplifying circuit complexity, facilitating high-density and high-speed non-volatile memory applications, and supporting fully-connected neural networks.
Implementation Method 1
lateral epitaxial growth of source/drain structures
Data Source
AI summary
A resistive memory structure is provided. The resistive memory structure includes a vertical fin on a substrate, wherein the sidewalls of the vertical fin each have a {100} crystal face. The resistive memory structure further includes a fin template on the vertical fin, and a gate structure on the vertical fin. The resistive memory structure further includes a top source/drain on opposite sidewalls of the vertical fin, and a bottom electrode layer on the top source/drain, wherein the bottom electrode layer is on opposite sides of the fin template. The resistive memory structure further includes a first middle resistive layer on a portion of the bottom electrode layer, a top electrode layer on the first middle resistive layer, and a first electrical contact on a portion of the bottom electrode layer.