Asymmetric Hard Mask for Split Gate Flash Memory ILD Filling
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Solution Overview
Problem
The formation of split gate flash memory cell devices with high aspect ratios leads to filling issues during the formation of the inter-layer dielectric (ILD) layer, resulting in voids and piping defects, and variations in the central region defined by lithography and etching can cause device failure.
Innovation Solution
The method involves forming split gate flash memory cell devices with hard masks having asymmetric profiles, which reduce the aspect ratio of the central region and utilize spacers to consistently define the central region, minimizing the likelihood of ILD filling issues and device failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the aspect ratio of the central region is high, then the device structure is more compact, but filling issues occur during ILD layer formation resulting in voids and piping defects
Solution Approach 1:
The patent divides the formation process into multiple stages: first forming the central region with high aspect ratio, then performing planarization to create a flatter surface, and finally filling the ILD layer. This segmentation allows the compact high aspect ratio structure to be maintained while eliminating filling defects through intermediate planarization steps.
Solution Approach 2:
The patent performs planarization as a preliminary action before ILD layer formation. By flattening the surface of the central region beforehand, the subsequent ILD filling process can proceed without voids or piping defects, even though the underlying structure maintains its compact high aspect ratio geometry.
2Ease of manufacture
If lithography and etching define the central region, then the manufacturing process is straightforward, but variations can cause device failure
Solution Approach 1:
The patent introduces a feedback mechanism where the results of lithography and etching are measured and evaluated, and subsequent planarization and spacer formation steps are adjusted based on this feedback to compensate for variations, ensuring consistent device performance despite process variations.
Solution Approach 2:
The patent changes physical parameters during processing: it performs planarization to alter surface topology, uses spacer formation to modify dimensional parameters, and adjusts material properties through selective deposition. These parameter changes compensate for lithography and etching variations, maintaining device reliability.
3Manufacturing precision
If spacers are used to define the central region, then definition accuracy improves, but device complexity increases
Solution Approach 1:
The patent introduces spacers as intermediary structures that mediate between the lithography-defined pattern and the final device geometry. These spacers provide precise dimensional control and serve as templates for subsequent etching steps, achieving high definition accuracy while keeping the overall fabrication approach systematic and manageable.
Data Source
AI summary
A semiconductor structure for a split gate flash memory cell device with a hard mask having an asymmetric profile is provided. In some embodiments, a semiconductor substrate of the semiconductor structure includes a first source/drain region and a second source/drain region. A control gate and a memory gate, of the semiconductor structure, are spaced over the semiconductor substrate between the first and second source/drain regions. A charge trapping dielectric structure of the semiconductor structure is arranged between neighboring sidewalls of the memory gate and the control gate, and arranged under the memory gate. A hard mask of the semiconductor structure is arranged over the control gate and includes an asymmetric profile. The asymmetric profile tapers in height away from the memory gate. A method for manufacturing a pair of split gate flash memory cell devices with hard masks having an asymmetric profile is also provided.