Recessed Gate DRAM Fabrication via Self-Aligned Spacers
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Solution Overview
Problem
Conventional planar transistor technology struggles to achieve high integration and miniaturization in DRAM fabrication due to the large surface area required, which limits the ability to meet demands for high memory capacity and operating speed.
Innovation Solution
The method involves forming a semiconductor device with a recessed gate by patterning a substrate and pad layers to create trenches, forming deep trench capacitors, and using spacers to etch a recess for the gate, allowing for precise control of the gate's position and reducing the need for photolithography, thereby enabling more efficient use of chip space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistor technology is used, then the transistor structure is simple to manufacture, but the surface area occupied by each transistor is large, limiting integration density
Solution Approach 1:
The patent transitions from planar (2D) transistor architecture to a three-dimensional recessed gate structure. The gate is formed extending into the substrate along the depth dimension, creating a vertical channel. This dimensional change allows the transistor to occupy less surface area while maintaining functional performance, directly resolving the contradiction between manufacturing simplicity and area efficiency.
Solution Approach 2:
The gate structure is nested within the substrate by forming a recess and placing the gate material inside it. This nesting approach allows the gate to be embedded in the substrate volume rather than occupying surface area, enabling higher integration density while keeping the overall device footprint small.
2Measurement precision
If photolithography is used for overlay control in conventional processes, then positioning can be achieved, but overlay control is very tight when process generation is 60 nm or further, making it difficult to control the distance between recessed gate and deep trench capacitor
Solution Approach 1:
The patent employs self-aligned fabrication processes where the spacer structures automatically define the position of the recessed gate relative to the deep trench capacitor. The spacers are formed conformally on the capacitor structures, and subsequent etching uses these spacers as alignment references. This self-service mechanism eliminates the need for separate photolithography overlay steps, achieving precise positioning without the tight overlay control limitations of conventional photolithography at 60 nm node and below.
Solution Approach 2:
The spacer structures serve as intermediary elements that mediate the positioning relationship between the deep trench capacitor and the recessed gate. These spacers are formed as a intermediate layer that physically defines the spacing and alignment, translating the capacitor structure position into the gate position without requiring direct photolithographic overlay control between the two features.
3Area of stationary object
If recessed gate technology is applied to reduce area, then integration density improves, but the fabrication process becomes more complex requiring additional steps
Solution Approach 1:
The patent merges multiple fabrication operations into integrated process sequences. The spacer formation, recess etching, and gate patterning are combined into a self-aligned flow where previous structures serve as templates for subsequent steps. This merging reduces the total number of separate lithography and etching cycles needed, mitigating the complexity increase that would otherwise result from the three-dimensional gate structure.
Solution Approach 2:
The patent performs preliminary actions by forming the spacer structures and defining the recess geometry before final gate material deposition. These preliminary structures are created with precise dimensions and positions that pre-determine the final gate location and shape. By establishing the geometric framework in advance through self-aligned spacer formation, the subsequent gate fabrication becomes a straightforward fill operation rather than a complex patterning step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of the gate's position and reduces the surface area occupied by transistors and capacitors, enhancing integration and reducing costs by eliminating one photolithography step, thus addressing the limitations of conventional technologies.
Implementation Method 1
The pad layer and the substrate are etched using the spacers and the deep trench capacitor devices as a mask to form a recess
Data Source
AI summary
A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor device is formed in each trench. The pad layer is recessed until upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions of the deep trench capacitor devices. The pad layer and the substrate are etched using the spacers and the deep trench capacitor devices as a mask to form a recess, and a recessed gate is formed in the recess.