Air Gap Formation in Nonvolatile Memory Gate Structures
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Solution Overview
Problem
Conventional semiconductor manufacturing processes result in high capacitance between gate lines in memory devices, affecting device performance.
Innovation Solution
A method and structure that includes forming a patterned metal gate layer on a substrate with a gate insulating layer, charge storage layer, and gate dielectric layer, followed by etching to create gate structures separated by spaces, and depositing an interlayer dielectric layer using PECVD to form air gaps, reducing capacitance between gate lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an interlayer dielectric layer is used to isolate gate lines, then the gate lines are isolated, but the capacitance between gate lines increases
Solution Approach 1:
The patent removes portions of the gate layer, gate dielectric layer, and charge storage layer to create spaces between gate structures. This extraction of material creates air gaps that eliminate the harmful dielectric material between gates, thereby reducing capacitance while maintaining gate isolation functionality.
Solution Approach 2:
The patent changes the physical state and material composition of the space between gate structures from solid dielectric material to air gaps. This parameter change from high-k dielectric material to air (low-k) reduces the capacitance between gate lines, directly addressing the technical contradiction.
2Productivity
If gate structures are placed close together, then device density increases, but capacitance between gate lines increases
Solution Approach 1:
The patent applies different properties to different regions: the gate structures themselves maintain high-k dielectric layers for charge storage functionality, while the spaces between gates are cleared to create air gaps. This local differentiation allows high device density while minimizing inter-gate capacitance through localized material removal.
Solution Approach 2:
The patent segments the continuous gate layer into discrete gate structures separated by spaces. This segmentation creates individual gate units with air gaps between them, allowing high density arrangement while reducing the harmful capacitive coupling that would exist in a continuous or closely-spaced structure.
3Object-affected harmful factors
If material is removed to create air gaps, then capacitance between gate lines decreases, but manufacturing complexity increases
Solution Approach 1:
The patent performs material removal operations during the gate formation process itself, before subsequent processing steps. By removing portions of the gate layer, gate dielectric layer, and charge storage layer while forming the patterned metal gate layer, the air gaps are created in advance, avoiding the need for additional dedicated etching steps later in the process.
Solution Approach 2:
The patent combines multiple functions into a single process step: the patterned metal gate layer formation serves both as the gate electrode patterning step and as the mask for creating air gaps between gates. This merging of functions reduces manufacturing complexity by eliminating separate etching steps that would otherwise be required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces coupling or fringe capacitance between gate lines, enhancing the performance of semiconductor devices by creating an air gap between gate stack structures.
Implementation Method 1
forming an interlayer dielectric layer on an upper surface of the gate structures stretching over the space while forming an air gap in the space. In one embodiment, forming the interlayer dielectric layer comprises a plasma-enhanced chemical vapor deposition (PECVD) process.
Data Source
AI summary
A method for manufacturing a semiconductor device includes providing a substrate structure having an active region, a gate insulating layer, a charge storage layer, a gate dielectric layer, and a gate layer sequentially formed on the active region. The method also includes forming a patterned metal layer on the substrate structure, removing a respective portion of the gate layer, the gate dielectric layer, the charge storage layer using the patterned metal gate layer as a mask to form multiple gate structures separated from each other by a space. The gate structures each include a stack containing a second portion of the charge storage layer, the gate dielectric layer, the gate layer, and one of the gate lines. The method further includes forming an interlayer dielectric layer on a surface of the gate structures stretching over the space while forming an air gap in the space.